RISC-V base ISA (RV32I - RV64I): Question bank — Hinglish deep dive

5.1.7 · D5 · Hardware › Instruction Set Architecture (ISA) › RISC-V base ISA (RV32I - RV64I)

Shuru karne se pehle, ek shared vocabulary reminder taaki neeche koi bhi word aisa na ho jo tune pin nahi kiya ho:

Definition Woh words jo baar baar chahiye honge

XLEN = ek register ki width in bits (aur program counter ki bhi). RV32I ke liye XLEN = 32, RV64I ke liye 64. Iska registers ki count se koi lena dena nahi.
pc (program counter) = ek special register jo us instruction ka memory address hold karta hai jo abhi chal rahi hai. Branches aur jumps ise kisi aur jagah point karne ke liye change karte hain.
==Zero register (x0)== = register number 0. Yeh hardwired to zero hai: ise read karne par hamesha 0 milta hai, aur koi bhi write silently throw away ho jaati hai. Kyunki yeh constant 0 ka ek permanent, free source hai, RISC-V ise bahut saare operations (move, load-zero, nop, compare-to-zero) banane ke liye reuse karta hai bina dedicated opcodes ke.
Sign-extend = ek chhote signed number ka top ("sign") bit leftward copy karna taaki ek wider box fill ho sake, aur ek negative value negative hi rahe. Dekho Two's Complement.
Immediate = ek constant number jo instruction bits mein hi baked in hota hai, register ya memory se nahi padha jaata.
Extension letter = RISC-V optional feature packs ko single letters se name karta hai jo I ke baad aate hain. M = Multiply/divide, A = atomics, F/D = floating point, C = Compressed (16-bit) instructions. Toh RV64IMC = 64-bit base + multiply + compressed.

Tum chhe instruction formats ke naam bhi miloge (R, I, S, B, U, J). Har ek ek fixed 32-bit template hai jo bits ko named fields mein kaata hai. Yahan un chaar ka vocabulary aur layout hai jo is page par aate hain:

Figure — RISC-V base ISA (RV32I - RV64I)

Ab teen pictures neeche ke almost har trap ko set up karti hain — pehle inhe dhyan se dekho.

True or false — justify

Kya RV32I aur RV64I mein registers ki count alag hoti hai?

False — dono mein exactly 32 general-purpose registers hote hain (x0–x31). Sirf har register ki width (XLEN) alag hoti hai: 32 vs 64 bits (dekho Picture 1).

"RV32I" mein "32" batata hai ki kitne registers exist karte hain.

False — woh "32" register width (XLEN) hai. Yeh ek pure coincidence hai ki register count bhi 32 hai; woh count RV32I aur RV64I dono mein fixed hai.

x0 mein koi value likhne se woh next instruction ke liye change ho jaati hai.

False — x0 zero register hai, hardwired to zero. Writes silently discard ho jaate hain aur reads hamesha 0 return karte hain; yahi ise constant zero ka free source banata hai (dekho vocabulary definition).

RISC-V ko ek dedicated "subtract immediate" instruction ki zaroorat hai.

False — immediates signed hote hain (Two's Complement), isliye addi rd, rs, -5 pehle se hi subtract kar deta hai. Ek addi dono directions cover karta hai kyunki sign-extend (Picture 2) negative field ko negative full-width value mein badal deta hai.

Har RV32I instruction same length ka hota hai.

True — sab base instructions exactly 32 bits ke hote hain. Fixed length ka matlab hai ki fetch aur decode trivial aur predictable hain, jo Pipelining mein help karta hai; chhe format templates (formats figure dekho) sab is width share karte hain.

RISC-V mein x86 jaisa flags register (carry, zero, overflow) hota hai.

False — koi flags register nahi hota. Jaise Picture 4 dikhata hai, ek branch instruction do registers seedha comparator mein feed karta hai aur result par jump karta hai, toh "kya woh match hue?" ka jawab kahin store karne ki zaroorat hi nahi (jaise bne x1, x0).

addi x0, x0, 0 ek genuinely useful instruction hai.

True — yeh kuch bhi observable nahi karta, jo exactly ek nop hai. Zero register (writes discarded) ek do-nothing instruction ko free mein banata hai.

RV64I ka addi 64-bit immediate use karta hai kyunki registers 64 bits ke hain.

False — immediate instruction mein abhi bhi 12 bits ka hi hai (I-type layout dekho); bas woh 32 ki jagah 64 bits tak sign-extend hota hai. Immediate field width aur XLEN independent hain.

Ek 20-bit J-type immediate se jal sirf

\pm 2^{19}

bytes tak hi jump kar sakta hai.

False — yeh tab sach hota agar field raw bytes count karta, lekin stored offset ka bit 0 implicit 0 hai, toh har step 2 bytes ka hai. Woh dropped bit wapas restore karne se reach

\pm 2^{20}

bytes (

\pm 1

MiB) tak double ho jaati hai, 2 ke steps mein (dekho Picture 3).

Spot the error

li x10, 0xEEF — kya yeh x10 mein 0xEEF chhod ta hai?

Error. 0xEEF ka bit 11 set hai, isliye ek signed 12-bit immediate ki tarah yeh negative hai aur 0xFFFF...FEEF tak sign-extend hota hai (Picture 2). Ek clean positive 0xEEF paane ke liye tumhe lui+addi pair chahiye.

"lui x10, 0xDEADB phir addi x10, x10, 0xEEF se 0xDEADBEEF milta hai." — sahi hai?

Error. 0xEEF ek negative add ki tarah sign-extend hota hai. Tumhe upper part ek se badhana padega (0xDEADB → 0xDEADC) taaki negative low add exactly 0xDEADBEEF par land kare. Yahi correction hai jo li pseudo-instruction automatically karta hai — dekho Assembler & Pseudo-instructions.

"S-type immediate sirf decoders ko confuse karne ke liye split ki gayi hai."

Error. Ek S-type ek store instruction hai (jaise sw); uski 12-bit immediate do pieces mein kati hai (bits 11:5 aur 4:0, formats figure mein dikhaya gaya hai) exactly isliye taaki rs1 aur rs2 fixed bit positions par rahe jo doosre formats ke saath shared hain. CPU tab registers padh sakta hai decode khatam hone se pehle — immediate reassembly MUX us speed ka chhota sa price hai.

"bne x1, x0, loop ko ek special compare-to-zero opcode chahiye."

Error. Aisa koi opcode exist nahi karta aur na hi zaroorat hai: x0 hi constant zero hai, isliye x0 ke against compare karne wala normal bne pehle se hi "nonzero hai toh branch karo" ka matlab deta hai (Picture 4 — comparator kaam karta hai).

"RV64I par, do 32-bit values par add sahi C int wrap-around deta hai."

Error. add full 64-bit registers par kaam karta hai aur 32 bits par wrap nahi karega. Tumhe addw chahiye, jo low 32 bits modulo

2^{32}

compute karta hai aur phir 64 bits tak sign-extend karta hai.

"Branch offset of imm = 1 target ko 1 byte aage move karta hai."

Error. Branch/jump offsets 2 bytes ke units mein hote hain (bit 0 implicit 0 hai). Sabse chhota nonzero step 2 bytes ka hai, jo instruction alignment se match karta hai (Picture 3).

Why questions

Constant-zero register (x0) itna accha design choice kyun hai?

Ek decision ek dozen special opcodes ki jagah le leta hai: mv, li 0, nop, aur compare-to-zero branches sab x0 use karne wale normal instructions mein reduce ho jaate hain.

RISC-V I-type immediate ko zero-extend ki jagah sign-extend kyun karta hai?

Taaki -1 jaisa negative chhota constant all-ones (0xFFFF...FF) ban jaaye aur arithmetic "just work" kare — subtraction aur negative offsets ke liye koi extra instructions nahi chahiye (Two's Complement).

Instructions ko CISC ki tarah variable length ki jagah fixed 32-bit kyun banaya?

Fixed length se fetch/decode trivial aur parallel ho jaata hai, jo Pipelining simplify karta hai. Yahi core RISC vs CISC trade hai: simpler hardware, compiler zyada kaam karta hai.

rs1/rs2/rd ko sab formats mein same bit positions par kyun rakha jaata hai?

Register file ko immediate decode hone se pehle read kiya ja sakta hai, jo pipeline se ek step hata deta hai. Fixed field positions ek deliberate speed-over-prettiness choice hai (I-, S-, B-, J-layouts formats figure mein compare karo — register fields line up karte hain).

RV64I mein manually masking ki jagah *w instructions kyun add kiye?

Woh ek instruction mein exact 32-bit modular arithmetic dete hain (phir sign-extend), taaki C ka int ek 64-bit machine par sahi behave kare bina manual masking ke.

Branch offset ka bit 0 implicit banane se reach double kyun ho jaati hai?

N bits ka ek field

2^{N}

alag values count karta hai. Agar woh values byte-offsets hain, toh reach

2^{N}

bytes hai. Lekin agar har stored value do bytes represent karta hai (kyunki dropped bit 0 hamesha 0 hai), toh same N bits ab

2 \times 2^{N}

bytes cover karte hain — bilkul free mein clean doubling (Picture 3).

RISC-V multiply/divide ko base I set se bahar kyun chhod ta hai?

Mandatory core ko tiny rakhne ke liye taaki har chip (tiny embedded se server tak) ise saste mein implement kar sake. Multiply/divide optional M (Multiply/divide) extension hai — tum RV32IM likhte ho jab koi chip ise include karta hai.

Edge cases

addi x0, x5, 100 actually kya karta hai?

Kuch bhi observable nahi — result x0 mein jaata, jiske writes discard ho jaate hain. Yeh effectively ek nop hai jo ek computed sum bhi waste karta hai.

Ek I-type immediate sabse badi aur sabse chhoti value kya hold kar sakta hai?

Ek 12-bit signed field mein

2^{12} = 4096

patterns hain, exactly aadhe aadhe divided: 2048 negative values (-2048 se -1 tak) aur 2048 non-negative values (0 se +2047 tak). Toh range hai -2048 se +2047 tak. Isse bahar kuch bhi lui+addi chahiye.

Kya ek single branch poore program mein kahin bhi reach kar sakta hai?

Nahi — B-type offsets sirf lagbhag plus-or-minus 4 KiB tak reach karte hain; exactly, target -4096 se +4094 bytes (sirf even addresses) tak ja sakta hai. Isse lambe control transfers ke liye jal (lagbhag plus-or-minus 1 MiB) ya jalr (register-relative, full range) use karo.

C (Compressed) extension "bit 0 is implicit 0" rule ke saath kaise interact karta hai?

C ke saath, instructions 16-bit ho sakte hain aur 2 bytes par align hote hain, isliye addresses abhi bhi even hain — sirf bit 0 guaranteed zero hai, bit 1 nahi. Isliye offsets 4 ki jagah 2 se scale hote hain; base ISA deliberately C ke liye yeh door open rakhta hai.

RV64I par, addw result produce karne ke baad top 32 bits kya hote hain?

Woh 32-bit result ke bit 31 ki sign-extension hote hain — us bit ki saari copies — taaki 64-bit register ek properly sign-extended 32-bit value hold kare.

Agar ek immediate ka top (sign) bit set hai, toh kya woh positive hai ya negative?

Negative — Two's Complement ke under, set most-significant bit ka matlab hai value zero se neeche hai. Exactly isliye 0xEEF (bit 11 set) -273 hai, +3823 nahi (Picture 2).

Agar tum lui mein aisi value daalte ho jisme 20 se zyada upper bits chahiye?

Ek instruction mein nahi ho sakta — lui sirf upper 20 bits (bits 31:12) fill karta hai. RV64I par bade constants ke liye additional shift/add steps chahiye, jo assembler tumhare liye expand karta hai.

Kya mv rd, rs ek real RISC-V opcode hai?

Nahi — yeh ek pseudo-instruction hai jo addi rd, rs, 0 mein assemble hoti hai. Dekho Assembler & Pseudo-instructions; hardware kabhi "move" opcode nahi dekhta.

Recall Teen villains, unke examples ke saath tied

Villain 1 — do "32"s (Picture 1): pehle do True/False items mein aata hai. Count = 32 hamesha; width = XLEN.
Villain 2 — signed 12-bit immediates (Picture 2): li x10, 0xEEF aur 0xDEADB-vs-0xDEADC errors ko drive karta hai. Bit 11 set matlab negative.
Villain 3 — offsets in units of 2 bytes (Picture 3): imm = 1, J-type range, aur C-extension items ke peeche. Bit 0 drop karne se reach double hoti hai.