Question bank — x86 architecture overview

x86 pehle chip se hi 64-bit tha. ::: False. 8086 16-bit tha; 32-bit 80386 ("IA-32") ke saath 1985 mein aaya aur 64-bit AMD64 ke saath 2003 mein hi aaya — teen decades ki growth, ek design nahi. AL mein likhne se AX mein stored value change hoti hai. ::: True is sense mein ki AL hi hai AX ka low byte (figure s01 dekho) — woh silicon share karte hain — toh AL badalne se jo tum AX se wapas padhoge woh bhi change ho jaata hai. Lekin AX ka high byte untouched rehta hai. Kyunki x86 CISC hai, isko kabhi utni efficiently pipeline nahi kiya ja sakta jitna RISC ko. ::: False. Modern x86 har CISC instruction ko RISC-jaise µops mein decode karta hai (figure s04) aur unhe out-of-order pipeline karta hai, toh internal engine RISC-ish hai chahe CISC face ho. "Segment × 16" ka matlab hai CPU har memory access par ek multiply run karta hai. ::: False. ×16 ek fixed left-shift hai 4 bits ka (figure s02), jo hardware mein sirf wires hain jo higher positions par route kiye gaye hain — koi multiplier nahi, essentially free hai. Modern 64-bit long mode mein, segment registers ab exist nahi karte. ::: False. Segmentation mostly disabled hai (flat memory), lekin CS, DS, SS, ES, FS, GS fossils ke roop mein exist karte hain — FS/GS toh thread-local storage ke liye actively use bhi hote hain. Ek x86 instruction ka har field optional hota hai. ::: False. Sirf opcode mandatory hai (figure s05 dekho); prefixes, ModR/M, SIB, displacement, aur immediate sab optional hain depending on kya instruction ko chahiye. Ek fixed-length RISC ISA instruction $n+1$ ko hamesha instruction $n$ finish hone se pehle decode kar sakta hai. ::: True — boundary ek known fixed stride par hoti hai (e.g. har 4 bytes), toh fetch unit ko immediately har start position pata hoti hai. x86 nahi kar sakta, kyunki use $n$ parse karna padta hai yeh jaanne ke liye ki $n$ kahan khatam hota hai. RAX aur EAX do alag registers hain jo tum independently use kar sakte ho. ::: False. EAX ek window hai single physical RAX ke low 32 bits par (figure s01). Ek hi storage cell hai, jo chaar widths par addressable hai (RAX/EAX/AX/AL).

"Ek x86 instruction 15 bytes tak ho sakti hai kyunki immediate field akele 15 bytes ka ho sakta hai." ::: Galat cause. 15-byte figure prefixes, opcode, ModR/M, SIB, displacement, aur immediate ka sum hai (figure s05); immediate akele zyada se zyada 8 bytes ka hota hai. Intel ne simply total ko 15 par cap kiya hai. "64-bit mode mein har immediate ek full 8-byte constant ho sakta hai." ::: Oversimplified. Zyaatar 64-bit-mode immediates abhi bhi sirf 4 bytes ke hote hain (32-bit, sign-extended to 64); akela common instruction jo full $8$-byte literal leta hai woh hai MOV r64, imm64. Isliye hi arbitrary 64-bit constants us ek MOV ko itna lamba banate hain. "8086 ko segmentation isliye chahiye tha kyunki 16-bit registers sirf 16 KB address kar sakte hain." ::: Arithmetic slip. 16 bits $2^{16}=64$ KB address karte hain, 16 KB nahi. Segmentation isliye chahiye tha taaki desired 20-bit / 1 MB space tak pahuncha ja sake, sirf 64 KB limit se bachne ke liye nahi. "AMD64 Intel ka 64-bit design tha, jo baad mein AMD ko license kiya gaya." ::: Reversed. AMD ne 64-bit extension design kiya (AMD64, 2003); Intel ne compatible version adopt kiya. Parent note exactly is trap ko flag karta hai. "Kyunki RCX counter register hai, CPU saare loops ko RCX use karne par force karta hai." ::: Overstated. RCX LOOP aur REP string ops ke liye traditional/implicit counter hai, lekin ordinary loops koi bhi general-purpose register use kar sakte hain. "PhysAddr = Offset × 16 + Segment." ::: Operands swapped. Segment hi shift hota hai: $(\text{Segment}\ll 4)+\text{Offset}$. Offset ko shift karna usse high bits mein galat jagah rakh deta. "REX prefix instructions ko 64-bit mode mein run karta hai opcode ko widen karke." ::: Galat mechanism. REX ek one-byte prefix hai ($\text{0x40}$–$\text{0x4F}$, opcode ka part nahi) jo 64-bit operand size select karta hai aur extra registers R8–R15 unlock karta hai.

Ek physical register ke chaar alag naam kyun hote hain (RAX/EAX/AX/AL)? ::: Kyunki register generations across extension se bada, har nayi width purani ko wrap karti gayi (figure s01); names tumhe usi fossilised cell ki kisi bhi nested layer ko address karne dete hain. Variable-length encoding CISC ka "fundamental tax" kyun hai? ::: Kyunki decoder ko instruction $n$ ko fully parse karna padta hai yeh jaanne ke liye ki instruction $n+1$ kahan shuru hoti hai, ek step ko serialize karta hai jo fixed-length RISC trivially parallel mein karta hai. Early CISC designers kyun dense, multi-step instructions chahte the? ::: Memory aur disk chhoti aur mehengi thi, toh kam instruction bytes ka matlab chhote programs aur sasta storage tha — RISC vs CISC dekho. Ek bada immediate constant physically instruction ko kyun lamba karta hai? ::: Constant instruction bytes ke andar hi baka hota hai (figure s05), toh ek 8-byte constant literally us instruction ki length mein 8 bytes add karta hai. Ek modern x86 chip 1980s ka DOS code kyun abhi bhi boot kar sakta hai? ::: Backward compatibility family ka top rule hai; nayi chips ne purani ISA ko extend kiya replace karne ki jagah, toh har legacy opcode abhi bhi decode hoti hai. Segmentation 16-bit numbers se 20-bit range kyun deta hai? ::: Segment ko 4 bits left shift karne se woh high bits mein stretch hota hai, 16-bit offset ke range se overlap karta hua: $20=16+4$ (figure s02). Parent x86 ko "CISC outside, RISC inside" kyun describe karta hai? ::: ISA jo programmer dekhta hai woh CISC hai, lekin microarchitecture usse µops mein translate karta hai aur unhe RISC-style run karta hai — do alag layers hain. Saare prefix families 15-byte cap ke andar kyun fit hote hain? ::: Kyunki Intel ek instruction ko zyada se zyada chaar prefix bytes tak limit karta hai total mein (operand-size, address-size, segment, lock/rep, REX combined), toh prefixes 15 ka ek bounded slice contribute karte hain.

Jab ek encoding 15 bytes exceed kare toh exactly kaun sa fault fire hota hai? ::: Ek #GP (General Protection fault) — decoder over-long encoding ko execute karne se pehle reject kar deta hai. (Ek alag fault, #UD, Undefined-opcode fault, illegal opcodes ke liye hai, over-length ke liye nahi; donon ko confuse mat karo.) 15 bytes hard ceiling hai, soft target nahi. Segment $=\text{0x0000}$ aur Offset $=\text{0x0000}$ ke saath physical address kya hai? ::: $\text{0x00000}$. Zero segment ka shift abhi bhi zero hai aur zero offset add karne se real-mode memory ka pehla byte hi milta hai. Do alag (segment, offset) pairs ek hi physical byte point kar sakte hain — kya ye bug hai? ::: Nahi, ye inherent aliasing hai (figure s03): kyunki segments har 16 bytes par overlap karte hain, $\text{0x1000:0x0000}$ aur $\text{0x0FFF:0x0010}$ dono $\text{0x10000}$ resolve karte hain. Real-mode programmers isi par rely karte the. Maximum real-mode physical address kya hai, aur kya woh 20 bits mein fit hota hai? ::: Max segment $\text{0xFFFF}$ aur offset $\text{0xFFFF}$ ke saath tum paate ho $\text{0xFFFF0}+\text{0xFFFF}=\text{0x10FFEF}$, jo 20 bits exceed karta hai — famous "A20 line" wrap-around jo 8086 exhibit karta tha. Agar kisi instruction mein koi memory operand nahi hai, toh kya usse abhi bhi ModR/M byte chahiye? ::: Hamesha nahi — register-only ya implicit-operand instructions ModR/M (aur isliye SIB) bilkul omit kar sakte hain, yahi exact reason hai ki lengths variable hain. x86-64 par, kya EAX mein likhna RAX ke upper 32 bits unchanged chodta hai, jaise AL karta hai AX ke saath? ::: Nahi — yahi trap hai (figure s01 mein red note dekho). EAX mein 32-bit write zero-extends, RAX ke top 32 bits clear karta hai, jabki 8- ya 16-bit write surrounding bits preserve karta hai. Ek fixed-width ISA jaise ARM ek 64-bit constant ko kaise handle karta hai jo ek instruction mein fit nahi hoti? ::: Woh usse inline nahi bake kar sakta; constant ko kai instructions mein build karta hai (e.g. MOVZ/MOVK) ya paas ke data pool se load karta hai — yahi price hai jo RISC fixed length ke liye pay karta hai. Kya Fetch-Decode-Execute Cycle khud x86 aur RISC par alag hota hai? ::: Cycle same hai fetch→decode→execute→write-back; sirf decode stage x86 par heavier hai kyunki use pehle instruction ki length determine karni padti hai aur usse µops mein split karna padta hai.