Exercises — Register file organization

KYA: hum sabse chhota $k$ chahte hain jis par $2^k\ge 16$ ho. KYU: har address bit se aap jo registers naam de sakte ho woh double ho jaata hai; aapko itne patterns chahiye ki har register ko ek unique naam mil sake. $k=\lceil {\log }_{2}16\rceil =\lceil 4\rceil =4\text{ bits.}$ Check karo: $2^4=16$ exactly, toh 4 bits se saare 16 registers ko naam milte hain, koi bacha nahi.

• Read = ek ==$2^k$-to-1 multiplexer== (MUX): bahut saare inputs, ek ko output wire par choose karo. Har read port ke liye ek MUX.
• Write = ek ==$k$-to-$2^k$ decoder== jiske outputs ek global WriteEnable ke saath AND hote hain: yeh exactly ek register ki capture line ko light up karta hai. YE DONO KYU, AUR KOI KYU NAHI? "Bahut saare mein se ek wire par choose karo" MUX ki definition hai; "ek wire ko bahut saare mein se ek ko bhejna" decoder ki definition hai. Ye dono ek doosre ke mirror image hain. Dekho Multiplexers and Decoders.

KYA: total state $=N\cdot n$. KYU: ports wiring/area ko affect karte hain, stored data ko nahi. Jo aap store kar sakte ho woh sirf (slots ki sankhya) × (har slot ki width) hai. $N\cdot n=32\times 64=2048\text{ bits.}$

KYA: har register field $k=5$ bits ka hai, aur 3 fields hain. $3\times k=3\times 5=15\text{ bits.}$ KYU YEH MATTER KARTA HAI: woh 15 bits tab hi khatam ho jaate hain jab aap opcode ke liye ek bhi bit nahi kharchte. Isliye $N$ badhana free nahi hai — yeh har instruction ko wide kar deta hai. Dekho Instruction Set Architecture (ISA).

KYA: area $\propto (R+W{)}^2$, aur $N,n$ unchanged hain toh woh cancel ho jaate hain. $\frac{(4+2{)}^2}{(2+1{)}^2}=\frac{6^2}{3^2}=\frac{36}{9}=4.$ YAISE DIKHTA HAI: grid figure mein, ports double karne se har cell ke through wire bundle mota ho jaata hai (zyada wires) aur har cell upar-neeche aur left-right bhi stretch hoti hai — height × width dono badhte hain, toh product square ke roop mein badhta hai. Chaar times bada, do times nahi.

KYA instruction maangta hai: add rd, rs1, rs2 ko ek hi cycle mein rs1 aur rs2 padhna hota hai (yeh 2 simultaneous reads hain) aur baad mein ek result rd mein store karna hota hai (1 write). KYU woh ports se map karta hai: ALU ke paas do operand inputs aur ek result output hai (dekho Datapath and ALU). Ek saath do operands read karna ⇒ $R=2$; ek result ⇒ $W=1$. Kam read ports se ALU apne doosre operand ka wait karte karte bhookha reh jaata. Kya badal deta hai: ek cycle mein zyada instructions issue karna (superscalar), ya 3 source operands wala instruction (e.g. fused multiply-add 3 padhta hai), $R$ ko upar push karta hai; ek cycle mein do results commit karna $W$ ko upar push karta hai. Har bump square ka cost lagata hai.

KYA hota hai timing policy par depend karta hai:

• Read-first: read port purana R5 value dekhta hai (write clock edge par land hoti hai, read sample kar chuka hone ke baad).
• Write-first / internal forwarding: nayi value ko read bus par steer kiya jaata hai, toh reader nayi R5 paata hai. KYU MATTER KARTA HAI: agar baad wali dependent instruction ko abhi-abhi compute ki gayi value chahiye aur file read-first hai bina kisi help ke, toh woh stale data padhti hai — ek data hazard. Real designs ek forwarding/bypass MUX add karte hain jo read address ko write address se compare karta hai aur, match hone par, fresh value seedha through feed karta hai. Dekho Pipeline Hazards.

KYA: har issued op ko 2 reads aur 1 write chahiye, aur 3 parallel mein issue hote hain. $R=3\times 2=6,W=3\times 1=3.$ Area factor: $\frac{(R+W{)}^2}{(2+1{)}^2}=\frac{(6+3{)}^2}{3^2}=\frac{81}{9}=9.$ KYU YEH REAL CHIPS KO SHAPE KARTA HAI: ek 3-wide file single-issue wali ki 9× area hai. Isliye wide machines aksar register file ko bank ya cluster karti hain — ise chhote copies mein split karo taaki har copy ke ports kam hon, square law se bachte huye. Yahi ek core reason hai ki superscalar design mushkil hai.

KYA trick aapko deti hai:

• mov rd, rs $\equiv$ add rd, rs, r0 kyunki $\text{rs}+0=\text{rs}$.
• nop $\equiv$ add r0, r0, r0 — yeh $0+0=0$ compute karta hai aur R0 mein write discard ho jaati hai, toh kuch nahi badlta. KYU YEH OPCODES BACHATA HAI: aap wahi ALU add reuse karte ho jo aapne already banaya hai; koi dedicated mov/nop opcode nahi chahiye, encoding space free hota hai (dekho RISC vs CISC). Hardware cost: basically kuch nahi — aap R0 ke liye flip-flops nahi banate; uska read-MUX input line low pe tied hota hai (constant 0), aur uski decoder line disconnect hai taaki writes gayab ho jaayein.

(a) Address width. $k=\lceil {\log }_{2}32\rceil =5$ bits. Kyun: $2^5=32$ saare registers ko naam deta hai, R0 samete (uska naam toh hai, bas hamesha 0 padhta hai). (b) Usable stored bits. Saare 32 slots ka naam hai lekin R0 ke flip-flops nahi hain, toh 31 real registers data store karte hain: $31\times 64=1984\text{ bits.}$ (Naive $32\times 64=2048$ ek aisa slot count karta hai jo kuch store nahi karta.) (c) add mein register-name bits. Teen fields, har ek $k=5$: $3\times 5=15$ bits. (d) Widening factor. $\frac{(4+2{)}^2}{(2+1{)}^2}=\frac{36}{9}=4$ — chaar times area.

Design A area (common $n$ drop karo): $A_A\propto N(R+W{)}^2=32\times (4+2{)}^2=32\times 36=1152.$ Design B area (do banks, unhe add karo): $A_B\propto 2\times [16\times (2+1{)}^2]=2\times (16\times 9)=2\times 144=288.$ Ratio: $A_A/A_B=1152/288=4$. Design B is 4× chhota is simplified model mein. KYU REALITY REFLECT KARTA HAI: banking square law se bachta hai har bank ka port count kam rakh kar. Catch yeh hai (area formula mein nahi): ek operand jo "wrong" bank mein hai woh cross-bank read force karta hai, toh real designs operands ko sahi bank mein schedule karni padti hain — ek genuine engineering trade-off. Dekho Datapath and ALU.

1. $N=16$ ⇒ kitne address bits? → $k=4$.
2. $N=32,n=64$, R0 hardwired ⇒ usable stored bits? → $31\times 64=1984$.
3. $R=2,W=1\to R=4,W=2$ jaane par area kitne times badha? → $36/9=4$.
4. 3-issue, 2R+1W each ⇒ $(R,W)$ aur area factor? → $R=6,W=3$; $81/9=9$.
5. Register file ko bank kyun karte hain? → ports-per-bank kam rakhne ke liye, $(R+W{)}^2$ square law se bachte huye.