Packaging and wire bonding - flip-chip: Worked examples

WHAT is this page? The parent note gave you two master formulas — perimeter wire-bond count $N_{wire} = 4 L / p$ and area-array flip-chip count $N_{flip} = (L / p)^{2}$ — plus the parasitic-inductance story $V = L \frac{d i}{d t}$ . Here we drill every corner case those formulas can be pushed into: tiny dies, giant dies, the exact crossover, a zero/degenerate input, a real product word-problem, and an exam-style twist. If a scenario can happen, it is worked below.

Before the examples, one habit from the parent topic: always say what a symbol means before using it. So, once, plainly:

The scenario matrix

Every question this topic can throw is one of these cells. Each example below is tagged with its cell.

Cell	Class of input	What is special about it	Example
A	Small die, $L ≲ 4 p$	Wire bonding still wins — the "underdog" regime	Ex 1
B	Crossover, $L = 4 p$ exactly	Boundary: the two methods tie	Ex 2
C	Large die, $L ≫ 4 p$	Flip-chip dominates hugely	Ex 3
D	Degenerate: $L \to 0$ or $p \to \infty$	$N \to 0$ — no room for any pad	Ex 4
E	Limiting: $p \to 0$	$N \to \infty$ in theory; where physics stops it	Ex 5
F	Real-world word problem	Choose a method for a given product	Ex 6
G	Electrical (parasitics)	Ground-bounce with signs & units	Ex 7
H	Exam twist	Rectangular die with mixed pitch $p_{x} \neq = p_{y}$	Ex 8

Ex 1 — Cell A: the small die where wire bonding wins

Worked example

A tiny sensor die is $L = 3 mm$ on a side, pad pitch $p = 1 mm$ . Count the I/O for each method. Which gives more connections?

Forecast: Guess first — with such coarse 1 mm pads, is the whole face worth using, or does the edge already hold everything?

Step 1. Wire bonding: $N_{wire} = \frac{4 L}{p} = \frac{4 \times 3}{1} = 12$ . Why this step? Each of the 4 edges holds $⌊ L / p ⌋ = 3$ pads; $4 \times 3 = 12$ . This is a 1-D (perimeter) resource. (Here $L / p = 3$ is already integer, so the floor changes nothing.)

Step 2. Flip-chip: $N_{flip} = (\frac{L}{p})^{2} = (\frac{3}{1})^{2} = 9$ . Why this step? The face is a $3 \times 3$ grid of bump sites. Because $L / p = 3$ is small, squaring it ( $9$ ) is less than multiplying by 4 ( $12$ ).

Step 3. Compare: $12 > 9$ , so wire bonding wins here. Why this step? When the die is only a few pitches wide, the perimeter (which has a factor of 4) beats the area (which squares a small number). This is the "wire bonding is not obsolete" mistake from the parent note, made concrete.

Verify: Sanity — look at the left panel of the figure below: a $3 \times 3$ bump grid vs pads all around the edge. Both counts are single-digit and close, exactly the regime where the choice is genuinely a toss-up. Units: $mm / mm$ is dimensionless, correct for a count.

Figure — Packaging and wire bonding - flip-chip

Figure: perimeter pads (burnt orange, around the rim) vs area-array bumps (deep teal, filling the face) for a $3 \times 3$ -pitch die. Count the orange dots (12) against the teal grid (9) — the edge wins when the die is small.

Ex 2 — Cell B: the exact crossover die

Worked example

At what die size $L$ (for a fixed pitch $p$ ) do the two methods give the same count? Then check $p = 0.25 mm$ .

Forecast: The parent note claimed the boundary is $L = 4 p$ . Predict: below it wire bonding leads, above it flip-chip. Let's earn that number.

Step 1. Set the counts equal: $(\frac{L}{p})^{2} = \frac{4 L}{p}$ . Why this step? "Tie" means equal I/O; equating the two formulas finds the switch-over.

Step 2. Let $x = L / p$ . Then $x^{2} = 4 x$ . Why this step? Substituting the ratio strips away units and turns a messy equation into a clean one in a single number $x$ .

Step 3. $x^{2} = 4 x \Rightarrow x^{2} - 4 x = 0 \Rightarrow x (x - 4) = 0$ , so $x = 0$ or $x = 4$ . Why this step? Factoring is legal here (we don't divide by $x$ blindly — that would hide the $x = 0$ root, which is the degenerate "no die" case of Cell D).

Step 4. Physical root: $x = 4$ , i.e. $L = 4 p$ . Why this step? $x = 0$ means a die of zero width (no chip) — mathematically valid, physically empty. The real crossover is $L = 4 p$ .

Step 5. For $p = 0.25 mm$ : crossover at $L = 4 \times 0.25 = 1 mm$ . Both give $N = 16$ . Why this step? Plug in: $4 L / p = 4 (1) /0.25 = 16$ and $(1/0.25)^{2} = 4^{2} = 16$ . They match — confirming the tie. Look at the crossover figure below: the two curves touch exactly at $x = 4$ .

Verify: Both formulas return $16$ , equal as required. And $x = 4$ is safely $> 0$ , so it is a genuine physical die.

Figure: the burnt-orange line is perimeter I/O ( $4 L / p$ , straight), the deep-teal curve is area I/O ( $(L / p)^{2}$ , bending upward). They cross where $L / p = 4$ (Cell B). Left of the plum line wire bonding leads (Cell A); right of it flip-chip runs away (Cell C).

Ex 3 — Cell C: the large die where flip-chip dominates

Worked example

A CPU die is $L = 20 mm$ , bump pitch $p = 0.15 mm$ . How many bumps? How badly does wire bonding lose?

Forecast: For a 2000-pin CPU, will the edge ever be enough? Guess the flip-chip number to the nearest thousand.

Step 1. Linear bump count per row: $⌊ L / p ⌋ = ⌊ 20/0.15 ⌋ = ⌊ 133.3 ⌋ = 133$ . Why this step? Apply the floor rule — you can't have a fractional bump, so round down to a whole number of sites that physically fit.

Step 2. Flip-chip: $N_{flip} = 13 3^{2} = 17, 689 \approx 17, 700$ . Why this step? Square the row count — a full 2-D grid over the whole face.

Step 3. Wire bonding: $N_{wire} = 4 \times 133 = 532$ . Why this step? Only the perimeter is usable; multiply the same linear count by 4, not by itself. (Exactly $532$ — no rounding needed here.)

Step 4. Ratio: $17, 689/532 \approx 33 \times$ more connections with flip-chip. Why this step? This is exactly why high-pin-count parts must use area arrays — the edge simply cannot hold enough pads.

Verify: $133/4 \approx 33$ , matching the ratio. Units dimensionless. The count exceeds 2000, so a 2000-pin CPU is feasible with flip-chip and impossible ( $532 < 2000$ ) with wire bonding.

Ex 4 — Cell D: degenerate inputs ( $L \to 0$ , $p$ huge)

Worked example

What happens to the counts as (a) the die shrinks to nothing, $L \to 0$ , and (b) the pitch grows past the die, $p > L$ ?

Forecast: Predict whether the formulas blow up or collapse. Which one hits zero first?

Step 1. As $L \to 0$ : $N_{wire} = 4 L / p \to 0$ and $N_{flip} = (L / p)^{2} \to 0$ . Why this step? Both formulas are proportional to positive powers of $L$ ; sending $L$ to zero sends both counts to zero — a die with no area holds no pads. Sensible.

Step 2. Note the rate: $N_{flip} \propto L^{2}$ vanishes faster than $N_{wire} \propto L^{1}$ . Why this step? Near $L = 0$ , squaring a tiny number is tinier still — this is the same reason wire bonding wins in Cell A, seen as a limit.

Step 3. Case $p = 2 mm$ , $L = 1 mm$ (pitch bigger than die): $N_{wire} = 4 (1) /2 = 2$ ; $N_{flip} = (1/2)^{2} = 0.25$ . Why this step? Plugging in shows the count drops below 1.

Step 4. Apply the floor rule: $⌊ L / p ⌋ = ⌊ 0.5 ⌋ = 0$ , so the honest flip-chip count is $0$ — not even one full bump fits. Why this step? A count must be a whole number $\geq 0$ ; a raw value under 1 means the geometry cannot host a single site. The formula still points the right way — it's telling you "impossible."

Verify: Both go to $0$ as $L \to 0$ ; with $p > L$ the flip-chip floor is $0$ , while wire bonding still fits $2$ edge pads — again the small-geometry regime where perimeter beats area. Consistent with Cell A.

Ex 5 — Cell E: the limiting case $p \to 0$

Worked example

The formulas say $N_{flip} = (L / p)^{2} \to \infty$ as $p \to 0$ . Does infinite I/O really happen? Where does physics stop it?

Forecast: Guess whether the wall is set by lithography, solder-ball physics, or heat.

Step 1. Mathematically, fix $L = 10 mm$ and shrink $p$ : at $p = 0.1$ , $N = 10, 000$ ; at $p = 0.01$ , $N = 1, 000, 000$ . Why this step? Halving the pitch quadruples the count — the $1/ p^{2}$ term explodes. On paper there is no limit.

Step 2. Physical wall #1 — bump collapse & bridging. Solder bumps have a minimum diameter; two bumps closer than ~their diameter reflow into one, shorting neighbours. Why this step? A short is an electrical failure, not a connection — so $p$ cannot go below roughly the bump size.

Step 3. Physical wall #2 — CTE stress. Tighter, smaller bumps carry more shear per bump when the die and board expand differently; below a pitch they crack even with underfill. Why this step? Connects the limit to a reliability failure mode, not just geometry.

Step 4. Physical wall #3 — routing & signal integrity. Even if bumps fit, the substrate must fan those thousands of nets out; escape routing runs out of layers. Why this step? The bottleneck moves from the die face to the package, so pitch is capped in practice at ~0.1 mm for mass production.

Verify: $N (p = 0.1) = (10/0.1)^{2} = 10, 000$ ✓ and $N (p = 0.01) = (10/0.01)^{2} = 1, 000, 000$ ✓. The math limit is $\infty$ ; the engineering limit is finite and set by the smallest of the three walls above.

Ex 6 — Cell F: real-world product decision

Worked example

You are packaging (a) a cheap 8-pin temperature sensor die, $L = 1.2 mm$ , and (b) a 1500-I/O GPU die, $L = 15 mm$ , both at an available pitch $p = 0.3 mm$ . Which method for each, and why?

Forecast: Predict before computing — does the 8-pin part even need an area array?

Step 1. Sensor required I/O = 8. Wire-bond capacity: $⌊ 1.2/0.3 ⌋ = 4$ pads/edge, so $4 \times 4 = 16 \geq 8$ . ✓ Why this step? Compare demand (8) to supply (16). The cheap perimeter method already has room to spare.

Step 2. Sensor flip-chip capacity: $⌊ 1.2/0.3 ⌋^{2} = 4^{2} = 16$ . Also enough — but flip-chip adds bumping + post-dicing underfill cost with no benefit at 8 pins. → Choose wire bonding. Why this step? When both methods clear the requirement, pick the cheaper one (the "superior ≠ cost-effective" mistake from the parent note).

Step 3. GPU required I/O = 1500. Wire-bond capacity: $4 \times ⌊ 15/0.3 ⌋ = 4 \times 50 = 200$ . $200 < 1500$ ✗ — impossible. Why this step? The edge simply cannot hold 1500 pads; this rules wire bonding out immediately.

Step 4. GPU flip-chip capacity: $⌊ 15/0.3 ⌋^{2} = 5 0^{2} = 2500 \geq 1500$ . ✓ → Choose flip-chip, which also gives the back-side heat-sink path a hot GPU needs. Why this step? Only the area array meets the pin count, and it bonus-solves cooling.

Verify: Sensor: $16 \geq 8$ (wire OK), $16 \geq 8$ (flip OK) → cost decides → wire bonding. GPU: $200 < 1500$ (wire fails), $2500 \geq 1500$ (flip works) → flip-chip. Both decisions follow from a single inequality each.

Ex 7 — Cell G: ground bounce with signs and units

Worked example

A supply net switches with $d i / d t = 0.5 A/ns$ . Compute the voltage droop for a wire bond ( $L = 2 nH$ ) and a flip-chip bump ( $L = 0.05 nH$ ). If the logic runs on $1 V$ , which survives?

Forecast: Guess how many volts a 2 nH wire droops — will it wreck a 1 V rail?

Step 1. Convert units cleanly: $d i / d t = 0.5 A/ns = 0.5/1 0^{- 9} = 5 \times 1 0^{8} A/s$ . Why this step? $V = L \frac{d i}{d t}$ needs SI: henries and amps-per-second, so we clear the "nano."

Step 2. Wire: $V = L \frac{d i}{d t} = (2 \times 1 0^{- 9}) (5 \times 1 0^{8}) = 1.0 V$ . Why this step? Faraday's law: a changing current through inductance $L$ makes a voltage that opposes the change (the sign says it fights the supply, i.e. a droop).

Step 3. Bump: $V = (0.05 \times 1 0^{- 9}) (5 \times 1 0^{8}) = 0.025 V$ . Why this step? Same law, 40× smaller inductance → 40× smaller droop.

Step 4. Compare to the $1 V$ rail: the wire's $1.0 V$ droop is 100% of the supply — logic collapses. The bump's $0.025 V$ is $2.5%$ — safe. Why this step? This is the concrete "electrical reason flip-chip wins" from the parent note.

Verify: Units: $H \cdot A/s = (V \cdot s/A) (A/s) = V$ ✓. Ratio of droops $1.0/0.025 = 40$ = ratio of inductances $2/0.05 = 40$ ✓.

Ex 8 — Cell H: exam twist — a rectangular die with mixed pitch

Worked example

Twist: the die is not square — it is $L_{x} = 12 mm$ by $L_{y} = 6 mm$ . Worse, the pitch differs by direction: bumps sit at $p_{x} = 0.2 mm$ across the $x$ -edges but $p_{y} = 0.3 mm$ across the $y$ -edges (a real constraint when one axis is routing-limited). The wire-bond pitch is the same $p_{x}, p_{y}$ on the matching edges. Derive and compute both counts.

Forecast: Predict which square formula gains a $2 (L_{x} + L_{y})$ and which gains a product of two different ratios — and whether mixed pitch helps or hurts.

Step 1. Wire bonding on a rectangle with mixed pitch: the two $x$ -length edges use pitch $p_{x}$ , the two $y$ -length edges use pitch $p_{y}$ . So $N_{wire} = 2 ⌊ \frac{L _{x}}{p _{x}} ⌋ + 2 ⌊ \frac{L _{y}}{p _{y}} ⌋ .$ Why this step? Wire bonding is a perimeter (1-D) resource; each pair of opposite edges gets its own pitch. There are two edges of length $L_{x}$ (spaced at $p_{x}$ ) and two of length $L_{y}$ (spaced at $p_{y}$ ).

Step 2. Flip-chip on a rectangle with mixed pitch: the face is a grid with $⌊ L_{x} / p_{x} ⌋$ columns and $⌊ L_{y} / p_{y} ⌋$ rows, so $N_{flip} = ⌊ \frac{L _{x}}{p _{x}} ⌋ \cdot ⌊ \frac{L _{y}}{p _{y}} ⌋ .$ Why this step? Flip-chip is an area (2-D) resource; the two axis pitches multiply, not square, because they now differ.

Step 3. Compute the floors: $⌊ 12/0.2 ⌋ = ⌊ 60 ⌋ = 60$ and $⌊ 6/0.3 ⌋ = ⌊ 20 ⌋ = 20$ . Why this step? Both ratios come out to whole numbers here, so the floor changes nothing — but we apply it as habit.

Step 4. Wire: $N_{wire} = 2 (60) + 2 (20) = 120 + 40 = 160$ . Why this step? Plug the two floors into the perimeter formula.

Step 5. Flip-chip: $N_{flip} = 60 \times 20 = 1200$ . Why this step? Plug the two floors into the area formula — the product of the two direction counts.

Step 6. Sanity — reduce to the simple cases. Set $p_{x} = p_{y} = p$ and $L_{x} = L_{y} = L$ : then $N_{wire} = 2 (2 L / p) = 4 L / p$ and $N_{flip} = (L / p) (L / p) = (L / p)^{2}$ — exactly the parent-note square formulas. ✓ Why this step? A good generalisation must collapse back to the special case; this proves we didn't break anything.

Verify: $2 (60) + 2 (20) = 160$ ✓; $60 \times 20 = 1200$ ✓. Flip-chip beats wire bonding by $1200/160 = 7.5 \times$ here, and the square-die reduction check passes. Note the mixed pitch hurt the $y$ -axis density (coarser $0.3$ mm), which is exactly why the flip-chip ratio is $7.5 \times$ rather than the $10 \times$ it would be at a uniform $0.2$ mm.

Active Recall

Recall Which cell wins for a die only 3 pitches wide, and why?

Cell A → wire bonding. With $L / p = 3$ , perimeter $4 \times 3 = 12$ beats area $3^{2} = 9$ ; squaring a small number loses to multiplying it by 4.

Recall What is the exact square-die crossover, and where does the second root come from?

$L = 4 p$ . Solving $x^{2} = 4 x$ gives $x (x - 4) = 0$ , so $x = 0$ (degenerate zero-width die) or $x = 4$ (the real crossover).

Recall What does the floor rule

$⌊ L / p ⌋$ enforce, and when does it matter? It forces an integer number of pads (no partial site). It matters whenever $L / p$ is not a whole number — e.g. $⌊ 133.3 ⌋ = 133$ , or $⌊ 0.5 ⌋ = 0$ (no bump fits at all).

Recall For a rectangular die with mixed pitch, what replaces

$4 L / p$ and $(L / p)^{2}$ ? $N_{wire} = 2 ⌊ L_{x} / p_{x} ⌋ + 2 ⌊ L_{y} / p_{y} ⌋$ (real perimeter) and $N_{flip} = ⌊ L_{x} / p_{x} ⌋ \cdot ⌊ L_{y} / p_{y} ⌋$ (real area); both reduce to the square forms when $L_{x} = L_{y}$ and $p_{x} = p_{y}$ .

Recall Why can't

$p \to 0$ give infinite I/O? Bump collapse/bridging, CTE shear cracking, and substrate escape-routing all cap the practical pitch near $0.1$ mm.