Exercises — Packaging and wire bonding - flip-chip

Method: wire bonding. The die is face-up, and "threads along the edges only" is the defining picture of perimeter wire bonding. Level: first-level interconnect — it connects the die to the package. (Second-level is package → PCB, e.g. a BGA of balls.)

The active face (the side with transistors and bumps) points down. The back of the die now faces up, leaving it exposed to bond a heat spreader — see Thermal Management and Heat Sinks.

The ultrasonic energy. The ~60–120 kHz vibration mechanically shears off the thin oxide/contaminant film. Thermal energy raises atomic mobility; mechanical energy increases true contact area; only ultrasonic removes the oxide barrier.

WHAT: plug into the perimeter formula. WHY: wires sit only on the 4 edges, and each edge of length $L$ holds $L/p$ pads. $N_{\text{wire}}=\frac{4L}{p}=\frac{4\times 8}{0.20}=\frac{32}{0.20}=160\text{ I/O.}$

WHAT: use the area formula. WHY: the face is a 2-D grid, $L/p$ bumps per row and $L/p$ rows. $N_{\text{flip}}={\left(\frac{L}{p}\right)}^2={\left(\frac{8}{0.20}\right)}^2=40^2=1600\text{ bumps.}$ Ten times the wire-bond count — because area beats perimeter.

WHAT: convert units, then apply $V=Ldi/dt$. WHY: a fast current change through inductance induces a back-voltage (Faraday's law) — this is exactly parasitic inductance biting. Convert: $0.3\text{A/ns}=0.3/10^{-9}=3\times 10^8\text{A/s}$, and $L=2\text{nH}=2\times 10^{-9}\text{H}$. $V=L\frac{di}{dt}=(2\times 10^{-9})(3\times 10^8)=0.6\text{V droop.}$ On a 1 V logic rail, a 0.6 V droop is catastrophic — this is why high-speed parts must avoid long wires.

WHAT we want: the crossover where $N_{\text{flip}}>N_{\text{wire}}$. ${\left(\frac{L}{p}\right)}^2>\frac{4L}{p}$ Step 1 — let $x=L/p$ (the die measured in pitches). This turns two variables into one, so we can compare cleanly: $x^2>4x$. Step 2 — divide by $x$. Since $L>0$ and $p>0$, $x>0$, so dividing by $x$ is legal and does not flip the inequality: $x>4$. Step 3 — translate back: $L/p>4\Rightarrow L>4p$. Meaning: for any die wider than 4 pad-pitches, area array wins — which is essentially every real chip.

$N_{\text{wire}}=\frac{4\times 10}{0.25}=160,N_{\text{flip}}={\left(\frac{10}{0.25}\right)}^2=40^2=1600.$ Ratio $=1600/160=10$. Why $L/(4p)$: dividing the formulas gives $\frac{N_{\text{flip}}}{N_{\text{wire}}}=\frac{(L/p{)}^2}{4L/p}=\frac{L}{4p}=\frac{10}{4\times 0.25}=10.✓$ The advantage grows linearly with die size — bigger chips reward flip-chip more.

WHY this formula: self-inductance = flux linked per unit current; the $\ln$ term comes from integrating the field $B={\mu }_{0}I/(2\pi \rho )$ across radial distance $\rho$ out from the wire. Precompute $\frac{{\mu }_0}{2\pi }=2\times 10^{-7}\text{H/m}$.

Wire A ($\ell =2\times 10^{-3}\text{m}$, $r=12.5\times 10^{-6}\text{m}$): $\frac{2\ell }{r}=\frac{4\times 10^{-3}}{12.5\times 10^{-6}}=320$, $\ln 320=5.768$, bracket $=5.768-0.75=5.018$. $L_A=2\times 10^{-7}\times 2\times 10^{-3}\times 5.018=2.01\times 10^{-9}\text{H}\approx 2.0\text{nH}.$

Wire B (bump) ($\ell =1\times 10^{-4}\text{m}$, $r=50\times 10^{-6}\text{m}$): $\frac{2\ell }{r}=\frac{2\times 10^{-4}}{50\times 10^{-6}}=4$, $\ln 4=1.386$, bracket $=1.386-0.75=0.636$. $L_B=2\times 10^{-7}\times 1\times 10^{-4}\times 0.636=1.27\times 10^{-11}\text{H}\approx 0.013\text{nH}.$ Ratio $L_A/L_B\approx 2.01\times 10^{-9}/1.27\times 10^{-11}\approx 158$. The 2 mm wire has ~160× the inductance of the bump — the quantitative heart of the parasitics argument.

(a) Set $N_{\text{flip}}=(L/p{)}^2=2000$. Solve for $p$: $\frac{L}{p}=\sqrt{2000}=44.72\Rightarrow p=\frac{L}{44.72}=\frac{18}{44.72}=0.4025\text{mm}.$ So a bump pitch of about $0.40\text{mm}$ delivers 2000 I/O — very relaxed, easily manufacturable. (b) At the same pitch $p=0.4025\text{mm}$, wire bonding gives $N_{\text{wire}}=\frac{4\times 18}{0.4025}=\frac{72}{0.4025}=178.9\approx 179\text{ I/O.}$ Only ~179 — hopeless for a 2000-pin part. To reach 2000 by perimeter alone would need $p=4L/N=72/2000=0.036\text{mm}$, a 36 µm pitch that is far beyond practical wire bonding. Conclusion: high-pin-count CPUs must be flip-chip.

The picture: silicon and the substrate expand by different amounts when heated (different CTE). Both grow outward from the die's centre. A bump's shear displacement is proportional to its distance from the neutral (centre) point — this is the DNP (Distance to Neutral Point) idea.

• A centre bump barely moves relative to its landing pad → tiny shear strain.
• A corner bump sits at the maximum distance → the die and substrate slide past each other the most there → maximum shear strain → it cracks first. Why underfill helps: the epoxy mechanically couples die and substrate over the whole area, redistributing that corner shear into the bulk so no single bump carries the full mismatch. Without it, corner bumps fatigue and open. (Related failure chemistry: Intermetallic Compounds and Bond Reliability.)

(a) $N_{\text{flip}}=(L/p{)}^2=900\Rightarrow L/p=\sqrt{900}=30\Rightarrow p=12/30=0.40\text{mm}$. Check the perimeter route at that pitch: $N_{\text{wire}}=4\times 12/0.40=120$ — far short of 900. So only flip-chip meets the I/O count at a sane pitch.

(b) Convert $di/dt=0.4\text{A/ns}=4\times 10^8\text{A/s}$.

• Wire: $V=(2.5\times 10^{-9})(4\times 10^8)=1.0\text{V}$ — a full-rail droop. Way over the 0.10 V budget.
• Bump: $V=(0.04\times 10^{-9})(4\times 10^8)=0.016\text{V}$ — well under 0.10 V. ✓

(c) Flip-chip wins on both counts. Wire bonding fails the I/O requirement (120 ≪ 900) and fails the noise budget (1.0 V ≫ 0.10 V). Flip-chip supplies 900 I/O at a comfortable 0.40 mm pitch and holds ground bounce to 0.016 V. This single problem reproduces the entire real-world logic: area-array I/O + low parasitic inductance = the two reasons high-performance silicon is flip-chip.

• Crossover die size for flip-chip to win (equal pitch)? ::: $L>4p$
• General I/O advantage ratio $N_{\text{flip}}/N_{\text{wire}}$? ::: $L/(4p)$
• Ground-bounce formula? ::: $V=Ldi/dt$
• Why do corner bumps fail first? ::: largest distance to neutral point → max CTE shear strain
• Why is inductance so much lower for a bump? ::: $L\propto \ell$, and a 0.1 mm bump is ~20× shorter than a 2 mm wire (and fatter), so far less flux linked