Exercises — Packaging and wire bonding - flip-chip

Method: wire bonding. Die face-up hai, aur "threads sirf edges ke along" — yeh perimeter wire bonding ki defining picture hai. Level: first-level interconnect — yeh die ko package se connect karta hai. (Second-level hai package → PCB, jaise BGA ke balls.)

Active face (woh side jisme transistors aur bumps hain) neeche ki taraf point karta hai. Die ki back ab upar ki taraf face karti hai, jo heat spreader bond karne ke liye exposed rehti hai — dekho Thermal Management and Heat Sinks.

Ultrasonic energy. ~60–120 kHz ki vibration mechanically patli oxide/contaminant film ko shear off kar deti hai. Thermal energy atomic mobility badhati hai; mechanical energy true contact area badhati hai; sirf ultrasonic hi oxide barrier ko remove karta hai.

KYA: perimeter formula mein plug in karo. KYUN: wires sirf 4 edges par hote hain, aur $L$ length ki har edge mein $L/p$ pads aate hain. $N_{\text{wire}}=\frac{4L}{p}=\frac{4\times 8}{0.20}=\frac{32}{0.20}=160\text{ I/O.}$

KYA: area formula use karo. KYUN: face ek 2-D grid hai, $L/p$ bumps per row aur $L/p$ rows. $N_{\text{flip}}={\left(\frac{L}{p}\right)}^2={\left(\frac{8}{0.20}\right)}^2=40^2=1600\text{ bumps.}$ Wire-bond count se das guna zyada — kyunki area, perimeter ko harata hai.

KYA: units convert karo, phir $V=Ldi/dt$ apply karo. KYUN: inductance ke through fast current change hone par back-voltage induce hoti hai (Faraday's law) — yahi parasitic inductance ka bite hai. Convert karo: $0.3\text{A/ns}=0.3/10^{-9}=3\times 10^8\text{A/s}$, aur $L=2\text{nH}=2\times 10^{-9}\text{H}$. $V=L\frac{di}{dt}=(2\times 10^{-9})(3\times 10^8)=0.6\text{V droop.}$ 1 V logic rail par, 0.6 V droop catastrophic hai — isliye high-speed parts mein long wires avoid karne chahiye.

KYA chahiye: woh crossover jahan $N_{\text{flip}}>N_{\text{wire}}$. ${\left(\frac{L}{p}\right)}^2>\frac{4L}{p}$ Step 1 — $x=L/p$ let karo (die ko pitches mein measure karna). Yeh do variables ko ek mein badal deta hai, taaki hum cleanly compare kar sakein: $x^2>4x$. Step 2 — $x$ se divide karo. Kyunki $L>0$ aur $p>0$ hain, $x>0$ hai, isliye $x$ se divide karna legal hai aur inequality flip nahi hoti: $x>4$. Step 3 — translate back karo: $L/p>4\Rightarrow L>4p$. Matlab: kisi bhi die ke liye jo 4 pad-pitches se wider ho, area array jeetta hai — jo essentially har real chip hai.

$N_{\text{wire}}=\frac{4\times 10}{0.25}=160,N_{\text{flip}}={\left(\frac{10}{0.25}\right)}^2=40^2=1600.$ Ratio $=1600/160=10$. $L/(4p)$ kyun: formulas divide karne par milta hai $\frac{N_{\text{flip}}}{N_{\text{wire}}}=\frac{(L/p{)}^2}{4L/p}=\frac{L}{4p}=\frac{10}{4\times 0.25}=10.✓$ Advantage die size ke saath linearly badhta hai — bade chips flip-chip ko aur zyada reward karte hain.

YEH FORMULA KYUN: self-inductance = flux linked per unit current; $\ln$ term wire se radial distance $\rho$ par field $B={\mu }_{0}I/(2\pi \rho )$ integrate karne se aata hai. Precompute $\frac{{\mu }_0}{2\pi }=2\times 10^{-7}\text{H/m}$.

Wire A ($\ell =2\times 10^{-3}\text{m}$, $r=12.5\times 10^{-6}\text{m}$): $\frac{2\ell }{r}=\frac{4\times 10^{-3}}{12.5\times 10^{-6}}=320$, $\ln 320=5.768$, bracket $=5.768-0.75=5.018$. $L_A=2\times 10^{-7}\times 2\times 10^{-3}\times 5.018=2.01\times 10^{-9}\text{H}\approx 2.0\text{nH}.$

Wire B (bump) ($\ell =1\times 10^{-4}\text{m}$, $r=50\times 10^{-6}\text{m}$): $\frac{2\ell }{r}=\frac{2\times 10^{-4}}{50\times 10^{-6}}=4$, $\ln 4=1.386$, bracket $=1.386-0.75=0.636$. $L_B=2\times 10^{-7}\times 1\times 10^{-4}\times 0.636=1.27\times 10^{-11}\text{H}\approx 0.013\text{nH}.$ Ratio $L_A/L_B\approx 2.01\times 10^{-9}/1.27\times 10^{-11}\approx 158$. 2 mm wire ki inductance bump se ~160× zyada hai — yeh parasitics argument ka quantitative core hai.

(a) Set karo $N_{\text{flip}}=(L/p{)}^2=2000$. $p$ ke liye solve karo: $\frac{L}{p}=\sqrt{2000}=44.72\Rightarrow p=\frac{L}{44.72}=\frac{18}{44.72}=0.4025\text{mm}.$ Toh ~$0.40\text{mm}$ ka bump pitch 2000 I/O deliver karta hai — bilkul relaxed, easily manufacturable. (b) Same pitch $p=0.4025\text{mm}$ par, wire bonding deta hai $N_{\text{wire}}=\frac{4\times 18}{0.4025}=\frac{72}{0.4025}=178.9\approx 179\text{ I/O.}$ Sirf ~179 — 2000-pin part ke liye hopeless. Sirf perimeter se 2000 reach karne ke liye $p=4L/N=72/2000=0.036\text{mm}$ chahiye hoga, 36 µm pitch jo practical wire bonding se bahut zyada hai. Conclusion: high-pin-count CPUs ko flip-chip hona hi padega.

Picture yeh hai: silicon aur substrate garam hone par alag-alag amounts se expand karte hain (alag CTE). Dono die ke centre se bahar ki taraf grow karte hain. Ek bump ka shear displacement uski neutral (centre) point se distance ke proportional hota hai — yeh DNP (Distance to Neutral Point) idea hai.

• Ek centre bump apne landing pad ke relative barely move karta hai → tiny shear strain.
• Ek corner bump maximum distance par hota hai → die aur substrate wahan sabse zyada ek doosre ke past slide karte hain → maximum shear strain → woh pehle crack karta hai. Underfill kyun help karta hai: epoxy mechanically die aur substrate ko poore area mein couple karta hai, us corner shear ko bulk mein redistribute karta hai taaki koi single bump full mismatch na uthaye. Iske bina, corner bumps fatigue hokar open ho jaate hain. (Related failure chemistry: Intermetallic Compounds and Bond Reliability.)

(a) $N_{\text{flip}}=(L/p{)}^2=900\Rightarrow L/p=\sqrt{900}=30\Rightarrow p=12/30=0.40\text{mm}$. Us pitch par perimeter route check karo: $N_{\text{wire}}=4\times 12/0.40=120$ — 900 se bahut kam. Toh sirf flip-chip I/O count meet karta hai ek sane pitch par.

(b) Convert karo $di/dt=0.4\text{A/ns}=4\times 10^8\text{A/s}$.

• Wire: $V=(2.5\times 10^{-9})(4\times 10^8)=1.0\text{V}$ — full-rail droop. 0.10 V budget se bahut zyada.
• Bump: $V=(0.04\times 10^{-9})(4\times 10^8)=0.016\text{V}$ — 0.10 V se kafi neeche. ✓

(c) Flip-chip dono mein jeetta hai. Wire bonding I/O requirement fail karta hai (120 ≪ 900) aur noise budget fail karta hai (1.0 V ≫ 0.10 V). Flip-chip 900 I/O comfortable 0.40 mm pitch par supply karta hai aur ground bounce 0.016 V par rakhta hai. Yeh single problem poori real-world logic reproduce karta hai: area-array I/O + low parasitic inductance = woh do reasons jis wajah se high-performance silicon flip-chip hoti hai.

• Flip-chip ke jeetnay ke liye crossover die size (equal pitch)? ::: $L>4p$
• General I/O advantage ratio $N_{\text{flip}}/N_{\text{wire}}$? ::: $L/(4p)$
• Ground-bounce formula? ::: $V=Ldi/dt$
• Corner bumps pehle kyun fail hote hain? ::: neutral point se sabse zyada distance → max CTE shear strain
• Bump ki inductance itni kam kyun hoti hai? ::: $L\propto \ell$, aur 0.1 mm bump, 2 mm wire se ~20× chhota hota hai (aur motaa bhi), isliye bahut kam flux link hoti hai