Packaging and wire bonding - flip-chip: Question bank

Definition Every symbol used on this page (read this first)

$L$ ::: the side length of the square die (the chip), e.g. $10 mm$ . Look at the black square in Figure 1 below — $L$ is one edge of it.
$p$ ::: the pitch, the centre-to-centre spacing between neighbouring pads/bumps (how tightly packed they are), e.g. $0.25 mm$ . Smaller $p$ = pads packed closer = more of them.
$ℓ$ ::: the length of a single interconnect (how long the wire or bump is from die to substrate). A wire loop is ~ $1 - 3 mm$ ; a bump is ~ $0.1 mm$ .
$r$ ::: the radius of the round bonding wire (half its thickness), ~ $15 - 33 μ m$ .
$L$ ::: the inductance of an interconnect — how strongly it opposes changes in current (measured in henries). Note the different script: we write $L$ (curly) for inductance so it never clashes with the die side $L$ (straight).
$ρ$ ::: the radial distance measured outward from the centre of the wire (the variable we integrate over when adding up magnetic flux); at the wire surface $ρ = r$ .
$I$ ::: the current flowing through the interconnect (in amperes).
$μ_{0}$ ::: the permeability of free space, a fixed constant of nature ( $\approx 1.26 \times 1 0^{- 6}$ ) that sets how strong a magnetic field a given current makes — it converts "current" into "magnetic field."
$E_{a}$ ::: the activation energy of bonding — the energy hump interfacial atoms must climb before they can interdiffuse and weld. Higher $E_{a}$ means the bond forms more slowly at a given temperature.
$k$ ::: Boltzmann's constant, the fixed number that converts temperature into a typical thermal energy per atom.
$T$ ::: absolute temperature (in kelvin) of the bond during bonding; $k T$ together is roughly "how much jiggling energy each atom has."

Figure 1 — Perimeter (1-D) vs area (2-D) I/O. Alt: a black die square with red pads only on its outline (wire bonding) beside a black die square with a red grid of bumps filling the whole face (flip-chip).

Figure 1 is the single mental model behind almost every trap on this page: wire bonding can only touch pads on the outline (the red perimeter, a 1-D resource), while flip-chip covers the whole area (the red grid, a 2-D resource). Keep it in view.

Figure 2 — Why flip-chip wins electrically. Alt: a tall wire-bond loop enclosing a large red-shaded area beside a short flip-chip bump (red) enclosing almost no area, over a black substrate line.

Figure 2 is the reason flip-chip wins electrically: the short bump links far less magnetic flux than the long wire loop, so its inductance $L$ is much smaller — refer to the red loop area as you read the inductance questions.

True or false — justify

True or false: Flip-chip always gives more usable I/O than wire bonding, for any die.

False. The area-array only beats the perimeter count once the die side

L

is wider than 4 pad-pitches (

L > 4 p

); a tiny die with very few pads gains nothing, and wire bonding is cheaper there.

True or false: In flip-chip the die's active (transistor) face points upward.

False. It is flipped face-down onto the substrate; the back of the die faces up, which is exactly what makes back-side cooling easy — the exposed back can take a heat spreader (heatsink, Thermal Management and Heat Sinks).

True or false: Once the solder bumps are reflowed, underfill epoxy is just optional extra glue.

False. Silicon and the substrate expand by different amounts when heated (a CTE mismatch); without underfill that mismatch shears the bumps apart over thermal cycles. Underfill spreads the stress and is essential — see Coefficient of Thermal Expansion (CTE) Mismatch.

True or false: More heat always produces a stronger wire bond.

False. Heat speeds diffusion, but too much oxidizes pads and grows brittle intermetallic compounds (the hard, cracky Au–Al "purple plague"); these weaken the joint — see Intermetallic Compounds and Bond Reliability. Bonding balances thermal + mechanical + ultrasonic energy, not a heat maximum.

True or false: A flip-chip joint has lower parasitic inductance than a wire bond mainly because solder conducts better than gold.

False. It is about length

ℓ

, not material: a ~

0.1 mm

bump is ~20× shorter than a ~

2 mm

wire, so it links far less magnetic flux and its inductance

L

drops (the electrical noise this causes is covered in Signal Integrity and Parasitic Inductance). Material choice is secondary.

True or false: Wire bonding is obsolete technology.

False. It is cheaper, skips the bumping and underfill steps, and dominates low/medium pin-count parts like microcontrollers, LEDs and sensors. Superior in I/O does not mean cost-effective everywhere.

True or false: Both wire bonding and flip-chip are "first-level interconnects."

True. Both connect the die to the package (first level). The package-to-PCB step (leads, balls, pins) is the separate second-level interconnect.

True or false: Ultrasonic scrubbing in bonding is there to add heat to the joint.

False. The ~60–120 kHz vibration shears off surface oxide and contaminants so clean metal meets clean metal; heat (the

k T

term) is a separate energy supplied thermally.

Spot the error

"Flip-chip scales linearly with die size just like wire bonding." — what's wrong?

Flip-chip uses the whole 2-D face, so it scales quadratically as

(L / p)^{2}

; wire bonding uses only the 1-D perimeter and scales linearly as

4 L / p

(here

L

is the die side,

p

the pad pitch). That difference is the entire reason flip-chip exists.

"A wire bond can be placed anywhere across the die surface." — what's wrong?

A wire bond reaches only pads along the perimeter (the die is glued face-up by its back); the interior is unreachable by wires. Area coverage is precisely the flip-chip advantage — see the red grid in Figure 1.

"Ground bounce comes from the wire's resistance." — what's wrong?

Ground bounce is a voltage droop

V = L \frac{d i}{d t}

driven by inductance during fast current changes, not resistance. A longer wire (bigger

ℓ

) means larger inductance and larger droop.

"Because flip-chip bumps are stronger than glue, the die needs no mechanical protection at all." — what's wrong?

The bumps hold the die but do not survive repeated CTE-driven shear; underfill epoxy is still required, and the whole assembly still needs encapsulation/protection like any package.

"Thermocompression bonding uses heat, force and ultrasonic energy." — what's wrong?

Thermocompression uses heat + force only. Adding all three (heat, force, ultrasonic) is thermosonic; force + vibration at room temperature is ultrasonic bonding.

"The 'C4' in C4 flip-chip stands for a type of solder alloy." — what's wrong?

C4 means Controlled Collapse Chip Connection — it describes how the bumps controllably collapse during reflow to form the joints, not an alloy.

"Increasing pad pitch

p

increases the I/O count." — what's wrong?

The pitch

p

is in the denominator of both

4 L / p

and

(L / p)^{2}

, so smaller pitch (pads packed closer) gives more I/O. Larger pitch reduces the count.

Why questions

Why does flip-chip give better electrical performance, not just more pins?

The joint is a ~

0.1 mm

vertical bump instead of a ~

1 - 3 mm

looping wire, so its length

ℓ

— and therefore both inductance

L

and resistance — drops sharply, giving cleaner power delivery and faster signals.

Why is the back-side access of flip-chip a thermal gift?

With the active face pointing down, the silicon back faces up and is free to bond directly to a heat spreader or heatsink, shortening the junction-to-ambient thermal path (see Thermal Management and Heat Sinks).

Why does the crossover condition come out as

L > 4 p

rather than some messy number?

Setting

(L / p)^{2} > 4 L / p

and dividing out one factor of

L / p

leaves

L / p > 4

. The "4" is simply the number of die edges wire bonding can use.

Why can't wire bonding serve a 2000-pin CPU?

Its count is limited to the perimeter

4 L / p

; even a

20 mm

die at fine pitch yields only a few hundred pads, far short of thousands. Only the area-array

(L / p)^{2}

reaches that many.

Why does the wire-bond inductance formula

L \approx \frac{μ _{0} ℓ}{2 π} [ln \frac{2 ℓ}{r} - 0.75]

contain a logarithm?

The magnetic field around the wire,

B = μ_{0} I / (2 π ρ)

(where

ρ

is the radial distance from the wire's centre and

I

the current), falls off like

1/ ρ

. Adding up (integrating) the linked flux from the wire surface

ρ = r

outward gives

\int d ρ / ρ = ln ρ

, and a logarithm is what you always get from a

1/ ρ

field.

Why do the integration limits in that inductance run from

r

to about

2 ℓ

(giving

ln (2 ℓ / r)

The lower limit is

ρ = r

because inside the metal (below the wire surface) the external-field formula does not apply — flux collection starts at the wire's edge. The upper limit is set by the wire's own length: the field lines close on the scale of the conductor, so the flux effectively stops being linked at a distance of order the wire length; the factor

2

falls out of the exact end-effect integration and gives the

2 ℓ

inside the log.

What is the constant

- 0.75

doing in that inductance formula?

It is a correction for the magnetic energy stored inside the wire's own metal (below

ρ = r

, where the external formula stops applying); for a round wire that internal contribution works out to a fixed

- 3/4 = - 0.75

, so it slightly reduces the total.

Why does thermosonic bonding combine three energies instead of just cranking one?

Each energy solves a different sub-problem — heat (raising

T

, so

k T

) increases atomic mobility (

\propto e^{- E_{a} / k T}

, where

E_{a}

is the activation-energy hump atoms must clear), force increases true contact area, ultrasonic removes oxide. Overdoing any one causes damage, so they are balanced.

Edge cases

Edge case: What happens to the flip-chip advantage as die side

L

shrinks toward

4 p

The quadratic and linear counts converge; at

L = 4 p

they are equal, and below it wire bonding actually offers as many or more pads at lower cost.

Edge case: A die has essentially only a handful of I/O (a simple discrete part). Which method wins?

Wire bonding. With so few pins the area-array gains nothing, and skipping bumping/underfill makes wire bonding decisively cheaper.

Edge case: Bump pitch

p

is made extremely small to pack more bumps. What limits go wrong?

Reliability degrades — closer, finer bumps concentrate CTE-mismatch shear stress, so underfill becomes even more critical and manufacturing/yield gets harder. More I/O is not free.

Edge case: If

d i / d t

during switching went to zero (DC, steady current), how much ground bounce appears?

None from inductance:

V = L \frac{d i}{d t} = 0

when current is constant. Inductive droop only appears during fast changes in current, which is why high-speed logic needs the low-inductance flip-chip path.

Edge case: A very large square die is bonded with only its four edges — does adding more area help wire bonding?

Only the added perimeter helps, so extra interior area is wasted for wire bonding; that untapped 2-D interior is exactly what flip-chip's area array exploits.

Edge case: Same die, same pitch, but you double the die side

L

. How do the two I/O counts respond?

Wire bonding doubles (

4 L / p

is linear); flip-chip quadruples (

(L / p)^{2}

is quadratic), widening the gap further as chips grow.

Recall One-line summary to carry away

Perimeter (1-D, linear $4 L / p$ ) vs area (2-D, quadratic $(L / p)^{2}$ ); face-down not up; underfill mandatory because of CTE; short $ℓ$ means low inductance $L$ ; and "better" is not the same as "cheaper for every product."