Packaging and wire bonding - flip-chip: Question bank

4.3.22 · D5 · Hardware › Semiconductor Fabrication › Packaging and wire bonding - flip-chip

Definition Is page par use kiye gaye har symbol ko pehle padho

$L$ ::: die ki square side length (chip), e.g. $10 mm$ . Neeche Figure 1 mein black square dekho — $L$ uska ek edge hai.
$p$ ::: pitch, neighbouring pads/bumps ke beech centre-to-centre spacing (kitne tightly packed hain), e.g. $0.25 mm$ . Chhota $p$ = pads zyada paas = zyada pads.
$ℓ$ ::: ek single interconnect ki length (wire ya bump die se substrate tak kitni lambi hai). Wire loop ~ $1 - 3 mm$ hoti hai; bump ~ $0.1 mm$ hota hai.
$r$ ::: round bonding wire ka radius (uski thickness ka aadha), ~ $15 - 33 μ m$ .
$L$ ::: interconnect ki inductance — yeh kitni strongly current mein changes ko oppose karta hai (henries mein measure hoti hai). Script ka difference note karo: inductance ke liye $L$ (curly) likhte hain taaki yeh die side $L$ (straight) se kabhi confuse na ho.
$ρ$ ::: wire ke centre se bahar measure ki gayi radial distance (woh variable jise hum magnetic flux add karte waqt integrate karte hain); wire surface par $ρ = r$ .
$I$ ::: interconnect mein flow karne wali current (amperes mein).
$μ_{0}$ ::: free space ki permeability, nature ka ek fixed constant ( $\approx 1.26 \times 1 0^{- 6}$ ) jo set karta hai ki ek given current kitna strong magnetic field banata hai — yeh "current" ko "magnetic field" mein convert karta hai.
$E_{a}$ ::: bonding ki activation energy — woh energy hump jo interfacial atoms ko interdiffuse aur weld hone se pehle climb karni padti hai. Zyada $E_{a}$ matlab bond ek given temperature par zyada slowly form hoga.
$k$ ::: Boltzmann's constant, woh fixed number jo temperature ko ek typical thermal energy per atom mein convert karta hai.
$T$ ::: bonding ke dauran bond ki absolute temperature (kelvin mein); $k T$ milke roughly "har atom ke paas kitni jiggling energy hai" hai.

Figure 1 — Perimeter (1-D) vs area (2-D) I/O. Alt: ek black die square jisme red pads sirf uski outline par hain (wire bonding), uske saath ek black die square jisme red bumps ka grid poora face fill karta hai (flip-chip).

Figure 1 is page par almost har trap ke peeche ka single mental model hai: wire bonding sirf outline par pads touch kar sakta hai (red perimeter, ek 1-D resource), jabki flip-chip poore area ko cover karta hai (red grid, ek 2-D resource). Ise dekhte raho.

Figure 2 — Flip-chip electrically kyun jeetta hai. Alt: ek tall wire-bond loop jo ek bada red-shaded area enclose karta hai, uske saath ek short flip-chip bump (red) jo almost koi area enclose nahi karta, ek black substrate line ke upar.

Figure 2 woh reason hai jis se flip-chip electrically jeetta hai: short bump far less magnetic flux link karta hai wire loop ki tulna mein, isliye uski inductance $L$ bahut chhoti hoti hai — inductance questions padhte waqt red loop area refer karo.

True or false — justify

True or false: Flip-chip hamesha wire bonding se zyada usable I/O deta hai, kisi bhi die ke liye.

False. Area-array perimeter count ko tabhi beat karta hai jab die side

L

4 pad-pitches se zyada wide ho (

L > 4 p

); ek tiny die jisme bahut kam pads hain usse kuch nahi milta, aur wahan wire bonding sasta hai.

True or false: Flip-chip mein die ki active (transistor) face upar ki taraf point karti hai.

False. Ise face-down substrate par flip kiya jaata hai; die ki back upar face karti hai, yahi cheez back-side cooling ko easy banati hai — exposed back par heat spreader (heatsink, Thermal Management and Heat Sinks) lag sakta hai.

True or false: Ek baar solder bumps reflow ho jaayein, underfill epoxy sirf optional extra glue hai.

False. Silicon aur substrate garam hone par alag-alag amounts mein expand hoti hain (CTE mismatch); underfill ke bina yeh mismatch thermal cycles mein bumps ko shear karke tod deta hai. Underfill stress spread karta hai aur zaroori hai — Coefficient of Thermal Expansion (CTE) Mismatch dekho.

True or false: Zyada heat hamesha ek stronger wire bond produce karti hai.

False. Heat diffusion speed karta hai, lekin zyada heat pads oxidize kar deti hai aur brittle intermetallic compounds (hard, cracky Au–Al "purple plague") grow karte hain; yeh joint ko weaken karte hain — Intermetallic Compounds and Bond Reliability dekho. Bonding thermal + mechanical + ultrasonic energy balance karti hai, heat maximum nahi.

True or false: Flip-chip joint mein wire bond se kam parasitic inductance hoti hai mainly kyunki solder gold se better conduct karta hai.

False. Yeh length

ℓ

ke baare mein hai, material nahi: ek ~

0.1 mm

bump ek ~

2 mm

wire se ~20× chhota hai, isliye yeh far less magnetic flux link karta hai aur uski inductance

L

drop hoti hai (yeh electrical noise Signal Integrity and Parasitic Inductance mein cover hai). Material choice secondary hai.

True or false: Wire bonding obsolete technology hai.

False. Yeh sasta hai, bumping aur underfill steps skip karta hai, aur low/medium pin-count parts jaise microcontrollers, LEDs aur sensors mein dominate karta hai. I/O mein superior hona har jagah cost-effective nahi hota.

True or false: Wire bonding aur flip-chip dono "first-level interconnects" hain.

True. Dono die ko package se connect karte hain (first level). Package-to-PCB step (leads, balls, pins) ek alag second-level interconnect hai.

True or false: Bonding mein ultrasonic scrubbing joint mein heat add karne ke liye hai.

False. ~60–120 kHz vibration surface oxide aur contaminants shear off karta hai taaki clean metal se clean metal mile; heat (woh

k T

term) ek alag energy hai jo thermally supply ki jaati hai.

Spot the error

"Flip-chip die size ke saath wire bonding ki tarah linearly scale karta hai." — kya galat hai?

Flip-chip poora 2-D face use karta hai, isliye yeh

(L / p)^{2}

ke hisaab se quadratically scale karta hai; wire bonding sirf 1-D perimeter use karta hai aur

4 L / p

ke hisaab se linearly scale karta hai (yahan

L

die side hai,

p

pad pitch). Yahi difference flip-chip ke exist karne ki poori wajah hai.

"Wire bond die surface ke kisi bhi jagah rakha ja sakta hai." — kya galat hai?

Wire bond sirf perimeter ke saath-saath pads tak pohunch sakta hai (die uski back se face-up chipka hoti hai); interior wire bonding se nahi pahuncha ja sakta. Area coverage precisely flip-chip ka advantage hai — Figure 1 mein red grid dekho.

"Ground bounce wire ki resistance se aata hai." — kya galat hai?

Ground bounce ek voltage droop

V = L \frac{d i}{d t}

hai jo fast current changes ke dauran inductance se drive hota hai, resistance se nahi. Ek lambi wire (bada

ℓ

) matlab zyada inductance aur zyada droop.

"Kyunki flip-chip bumps glue se zyada strong hain, die ko bilkul koi mechanical protection nahi chahiye." — kya galat hai?

Bumps die ko hold karte hain lekin repeated CTE-driven shear survive nahi karte; underfill epoxy phir bhi zaroori hai, aur poori assembly ko phir bhi encapsulation/protection chahiye jaise kisi bhi package ko.

"Thermocompression bonding heat, force aur ultrasonic energy use karta hai." — kya galat hai?

Thermocompression sirf heat + force use karta hai. Teeno milana (heat, force, ultrasonic) thermosonic hai; room temperature par force + vibration ultrasonic bonding hai.

"C4 flip-chip mein 'C4' ek type ke solder alloy ka naam hai." — kya galat hai?

C4 ka matlab hai Controlled Collapse Chip Connection — yeh describe karta hai ki bumps reflow ke dauran controllably collapse karke joints form karte hain, koi alloy nahi.

"Pad pitch

p

badhane se I/O count badh jaata hai." — kya galat hai?

Pitch

p

dono

4 L / p

aur

(L / p)^{2}

ke denominator mein hai, isliye chhota pitch (pads zyada paas packed) zyada I/O deta hai. Bada pitch count reduce karta hai.

Why questions

Flip-chip better electrical performance kyun deta hai, sirf zyada pins nahi?

Joint ek ~

0.1 mm

vertical bump hai ek ~

1 - 3 mm

looping wire ki jagah, isliye uski length

ℓ

— aur isliye inductance

L

aur resistance dono — sharply drop hoti hai, cleaner power delivery aur faster signals dete hain.

Flip-chip ka back-side access thermally ek gift kyun hai?

Active face neeche point karne se, silicon back upar face karta hai aur seedha heat spreader ya heatsink se bond karne ke liye free hota hai, junction-to-ambient thermal path chhota karta hai (Thermal Management and Heat Sinks dekho).

Crossover condition

L > 4 p

kyun aata hai, koi messy number kyun nahi?

(L / p)^{2} > 4 L / p

set karke aur

L / p

ka ek factor divide out karne se

L / p > 4

bachta hai. "4" simply wire bonding ke use karne wale die edges ki sankhya hai.

Wire bonding ek 2000-pin CPU ko kyun serve nahi kar sakta?

Uska count perimeter

4 L / p

tak limited hai; even ek

20 mm

die fine pitch par sirf kuch hundred pads deta hai, hazaron se bahut kam. Sirf area-array

(L / p)^{2}

utne tak pohunch sakta hai.

Wire-bond inductance formula

L \approx \frac{μ _{0} ℓ}{2 π} [ln \frac{2 ℓ}{r} - 0.75]

mein logarithm kyun hai?

Wire ke aas-paas magnetic field,

B = μ_{0} I / (2 π ρ)

(jahan

ρ

wire ke centre se radial distance hai aur

I

current hai),

1/ ρ

ki tarah fall off karta hai. Wire surface

ρ = r

se bahar linked flux add up karne (integrate karne) se

\int d ρ / ρ = ln ρ

milta hai, aur ek logarithm hamesha wahi milta hai jo

1/ ρ

field se milta hai.

Us inductance mein integration limits

r

se roughly

2 ℓ

tak kyun jaati hain (jo

ln (2 ℓ / r)

deta hai)?

Lower limit

ρ = r

hai kyunki metal ke andar (wire surface ke neeche) external-field formula apply nahi hota — flux collection wire ke edge par shuru hoti hai. Upper limit wire ki apni length se set hoti hai: field lines conductor ki scale par close hoti hain, isliye flux effectively wire length ke order ki distance par linked hona band ho jaata hai; factor

2

exact end-effect integration se aata hai aur log ke andar

2 ℓ

deta hai.

Us inductance formula mein constant

- 0.75

kya kar raha hai?

Yeh magnetic energy ke liye correction hai jo wire ke apne metal ke andar store hoti hai (

ρ = r

ke neeche, jahan external formula apply hona band ho jaata hai); ek round wire ke liye woh internal contribution ek fixed

- 3/4 = - 0.75

nikalta hai, isliye yeh total ko thoda reduce karta hai.

Thermosonic bonding teen energies kyun combine karta hai, sirf ek ko crank karne ki jagah?

Har energy ek alag sub-problem solve karti hai — heat (

T

badhana, so

k T

) atomic mobility badhata hai (

\propto e^{- E_{a} / k T}

, jahan

E_{a}

woh activation-energy hump hai jo atoms ko clear karni padti hai), force true contact area badhata hai, ultrasonic oxide remove karta hai. Kisi ek ko overdoing karne se damage hota hai, isliye inhe balance kiya jaata hai.

Edge cases

Edge case: Die side

L

jaise

4 p

ki taraf shrink karta hai flip-chip advantage ka kya hota hai?

Quadratic aur linear counts converge ho jaate hain;

L = 4 p

par woh equal hain, aur usse neeche wire bonding utne ya zyada pads kam cost mein deta hai.

Edge case: Ek die mein essentially sirf handful I/O hain (ek simple discrete part). Kaun sa method jeetta hai?

Wire bonding. Itne kam pins ke saath area-array kuch gain nahi karta, aur bumping/underfill skip karna wire bonding ko decisively sasta banata hai.

Edge case: Zyada bumps pack karne ke liye bump pitch

p

bahut chhota kar diya jaata hai. Kaun si limits galat ho jaati hain?

Reliability degrade hoti hai — zyada paas, finer bumps CTE-mismatch shear stress concentrate karte hain, isliye underfill aur bhi critical ho jaata hai aur manufacturing/yield mushkil hoti hai. Zyada I/O free nahi hota.

Edge case: Agar switching ke dauran

d i / d t

zero ho jaaye (DC, steady current), kitna ground bounce appear hota hai?

Inductance se kuch nahi:

V = L \frac{d i}{d t} = 0

jab current constant ho. Inductive droop sirf current mein fast changes ke dauran appear hota hai, yahi wajah hai ki high-speed logic ko low-inductance flip-chip path chahiye.

Edge case: Ek bahut bada square die sirf apne chaar edges se bond kiya gaya hai — kya zyada area add karne se wire bonding mein help hoti hai?

Sirf added perimeter help karta hai, isliye extra interior area wire bonding ke liye waste hai; yahi untapped 2-D interior hai jo flip-chip ki area array exactly exploit karti hai.

Edge case: Same die, same pitch, lekin die side

L

double kar do. Dono I/O counts kaise respond karte hain?

Wire bonding double hota hai (

4 L / p

linear hai); flip-chip quadruple hota hai (

(L / p)^{2}

quadratic hai), gap aur bhi badata hai jaise chips grow karte hain.

Recall Ek-line summary jo saath le jaao

Perimeter (1-D, linear $4 L / p$ ) vs area (2-D, quadratic $(L / p)^{2}$ ); face-down na ki upar; underfill CTE ki wajah se mandatory; chhota $ℓ$ matlab kam inductance $L$ ; aur "better" ka matlab "har product ke liye sasta" nahi hota.