Packaging and wire bonding - flip-chip: Worked examples

4.3.22 · D3 · Hardware › Semiconductor Fabrication › Packaging and wire bonding - flip-chip

YE PAGE KYA HAI? Parent note ne tumhe do master formulas diye the — perimeter wire-bond count $N_{wire} = 4 L / p$ aur area-array flip-chip count $N_{flip} = (L / p)^{2}$ — saath mein parasitic-inductance ki kahani $V = L \frac{d i}{d t}$ . Yahan hum har corner case ko drill karte hain jahan ye formulas push ho sakti hain: tiny dies, giant dies, exact crossover, ek zero/degenerate input, ek real product word-problem, aur ek exam-style twist. Agar koi scenario ho sakta hai, woh neeche worked out hai.

Examples se pehle, parent topic se ek aadat: koi bhi symbol use karne se pehle uska matlab batao. Toh, ek baar, seedha saaf:

Scenario matrix

Is topic ka har sawal inhi cells mein se ek hoga. Neeche har example apni cell ke saath tagged hai.

Cell	Input ki class	Usmein kya khaas hai	Example
A	Chota die, $L ≲ 4 p$	Wire bonding abhi bhi jeet raha hai — "underdog" regime	Ex 1
B	Crossover, $L = 4 p$ exactly	Boundary: dono methods tie karte hain	Ex 2
C	Bada die, $L ≫ 4 p$	Flip-chip hugely dominate karta hai	Ex 3
D	Degenerate: $L \to 0$ ya $p \to \infty$	$N \to 0$ — kisi bhi pad ke liye jagah nahi	Ex 4
E	Limiting: $p \to 0$	Theory mein $N \to \infty$ ; physics kahan rokti hai	Ex 5
F	Real-world word problem	Ek given product ke liye method choose karo	Ex 6
G	Electrical (parasitics)	Ground-bounce with signs & units	Ex 7
H	Exam twist	Rectangular die with mixed pitch $p_{x} \neq = p_{y}$	Ex 8

Ex 1 — Cell A: chota die jahan wire bonding jeet ta hai

Worked example

Ek tiny sensor die $L = 3 mm$ side ka hai, pad pitch $p = 1 mm$ . Dono methods ke liye I/O count karo. Kaun zyada connections deta hai?

Forecast: Pehle guess karo — itne coarse 1 mm pads ke saath, kya poori face worth using hai, ya edge already sab kuch hold kar leti hai?

Step 1. Wire bonding: $N_{wire} = \frac{4 L}{p} = \frac{4 \times 3}{1} = 12$ . Ye step kyun? Har 4 edges mein se ek $⌊ L / p ⌋ = 3$ pads hold karti hai; $4 \times 3 = 12$ . Yeh ek 1-D (perimeter) resource hai. (Yahan $L / p = 3$ already integer hai, toh floor kuch nahi badalta.)

Step 2. Flip-chip: $N_{flip} = (\frac{L}{p})^{2} = (\frac{3}{1})^{2} = 9$ . Ye step kyun? Face ek $3 \times 3$ grid of bump sites hai. Kyunki $L / p = 3$ chota hai, ise square karna ( $9$ ) se 4 se multiply karne ( $12$ ) se kam milta hai.

Step 3. Compare: $12 > 9$ , toh wire bonding yahan jeet ta hai. Ye step kyun? Jab die sirf kuch pitches wide ho, toh perimeter (jisme 4 ka factor hai) area ko (jo ek chote number ko square karta hai) beat kar deta hai. Yeh parent note ki "wire bonding obsolete nahi hai" wali galti hai, concrete form mein.

Verify: Sanity — neeche figure ka left panel dekho: $3 \times 3$ bump grid vs edge ke around pads. Dono counts single-digit aur close hain, exactly woh regime jahan choice genuinely toss-up hai. Units: $mm / mm$ dimensionless hai, count ke liye correct.

Figure — Packaging and wire bonding - flip-chip

Figure: perimeter pads (burnt orange, rim ke around) vs area-array bumps (deep teal, face fill karte hue) ek $3 \times 3$ -pitch die ke liye. Orange dots (12) count karo teal grid (9) se compare karo — jab die choti ho toh edge jeetti hai.

Ex 2 — Cell B: exact crossover die

Worked example

Kisi fixed pitch $p$ ke liye die size $L$ kitni ho jab dono methods same count den? Phir $p = 0.25 mm$ check karo.

Forecast: Parent note ne claim kiya tha ki boundary $L = 4 p$ hai. Predict karo: uske neeche wire bonding lead karta hai, uske upar flip-chip. Chaliye wo number earn karte hain.

Step 1. Counts equal set karo: $(\frac{L}{p})^{2} = \frac{4 L}{p}$ . Ye step kyun? "Tie" ka matlab equal I/O; dono formulas ko equate karne se switch-over milta hai.

Step 2. $x = L / p$ rakho. Toh $x^{2} = 4 x$ . Ye step kyun? Ratio substitute karne se units hat jaate hain aur ek messy equation ek clean equation ban jaati hai single number $x$ mein.

Step 3. $x^{2} = 4 x \Rightarrow x^{2} - 4 x = 0 \Rightarrow x (x - 4) = 0$ , toh $x = 0$ ya $x = 4$ . Ye step kyun? Factoring yahan valid hai (hum blindly $x$ se divide nahi karte — aise karne se $x = 0$ root chhuup jaata, jo Cell D ka degenerate "no die" case hai).

Step 4. Physical root: $x = 4$ , yaani $L = 4 p$ . Ye step kyun? $x = 0$ ka matlab zero width ka die (koi chip nahi) — mathematically valid, physically empty. Real crossover $L = 4 p$ hai.

Step 5. $p = 0.25 mm$ ke liye: crossover $L = 4 \times 0.25 = 1 mm$ par. Dono $N = 16$ dete hain. Ye step kyun? Plug in karo: $4 L / p = 4 (1) /0.25 = 16$ aur $(1/0.25)^{2} = 4^{2} = 16$ . Match karte hain — tie confirm. Neeche crossover figure dekho: dono curves exactly $x = 4$ par touch karti hain.

Verify: Dono formulas $16$ return karti hain, equal as required. Aur $x = 4$ safely $> 0$ hai, toh yeh genuinely physical die hai.

Figure: burnt-orange line perimeter I/O hai ( $4 L / p$ , straight), deep-teal curve area I/O hai ( $(L / p)^{2}$ , upar ki taraf bend karti). Yeh cross karte hain jahan $L / p = 4$ (Cell B). Plum line ke baayein wire bonding lead karta hai (Cell A); daayein flip-chip bhag jaata hai (Cell C).

Ex 3 — Cell C: bada die jahan flip-chip dominate karta hai

Worked example

Ek CPU die $L = 20 mm$ hai, bump pitch $p = 0.15 mm$ . Kitne bumps? Wire bonding kitna badly haarta hai?

Forecast: 2000-pin CPU ke liye, kya edge kabhi enough hogi? Flip-chip number nearest thousand tak guess karo.

Step 1. Linear bump count per row: $⌊ L / p ⌋ = ⌊ 20/0.15 ⌋ = ⌊ 133.3 ⌋ = 133$ . Ye step kyun? Floor rule apply karo — fractional bump nahi ho sakta, toh physically fit hone wale whole number of sites tak round down karo.

Step 2. Flip-chip: $N_{flip} = 13 3^{2} = 17, 689 \approx 17, 700$ . Ye step kyun? Row count square karo — poori face par full 2-D grid.

Step 3. Wire bonding: $N_{wire} = 4 \times 133 = 532$ . Ye step kyun? Sirf perimeter usable hai; same linear count ko 4 se multiply karo, khud se nahi. (Exactly $532$ — yahan koi rounding nahi.)

Step 4. Ratio: $17, 689/532 \approx 33 \times$ zyada connections flip-chip se. Ye step kyun? Isliye hi high-pin-count parts zaroor area arrays use karte hain — edge simply enough pads hold nahi kar sakti.

Verify: $133/4 \approx 33$ , ratio se match karta hai. Units dimensionless. Count 2000 se zyada hai, toh 2000-pin CPU flip-chip se feasible hai aur wire bonding se impossible ( $532 < 2000$ ).

Ex 4 — Cell D: degenerate inputs ( $L \to 0$ , $p$ huge)

Worked example

Counts ka kya hota hai jab (a) die kuch nahi ban jaati, $L \to 0$ , aur (b) pitch die se badi ho jaati hai, $p > L$ ?

Forecast: Predict karo ki formulas blow up hongi ya collapse. Kaun pehle zero hit karti hai?

Step 1. Jab $L \to 0$ : $N_{wire} = 4 L / p \to 0$ aur $N_{flip} = (L / p)^{2} \to 0$ . Ye step kyun? Dono formulas $L$ ki positive powers ke proportional hain; $L$ ko zero bhejne se dono counts zero ho jaati hain — zero area wali die mein koi pad nahi ho sakta. Sensible hai.

Step 2. Rate note karo: $N_{flip} \propto L^{2}$ , $N_{wire} \propto L^{1}$ se zyada tezi se vanish hota hai. Ye step kyun? $L = 0$ ke paas, ek tiny number ko square karna aur bhi tiny ho jaata hai — yahi wajah hai ki Cell A mein wire bonding jeetता hai, ek limit ke roop mein dekha gaya.

Step 3. Case $p = 2 mm$ , $L = 1 mm$ (pitch die se badi): $N_{wire} = 4 (1) /2 = 2$ ; $N_{flip} = (1/2)^{2} = 0.25$ . Ye step kyun? Plug in karne se pata chalta hai count 1 se neeche gir jaati hai.

Step 4. Floor rule apply karo: $⌊ L / p ⌋ = ⌊ 0.5 ⌋ = 0$ , toh honest flip-chip count $0$ hai — ek bhi full bump fit nahi hota. Ye step kyun? Count ek whole number $\geq 0$ hona chahiye; 1 se kam raw value ka matlab hai geometry single site host nahi kar sakti. Formula phir bhi sahi direction point karta hai — yeh bata raha hai "impossible."

Verify: Dono $L \to 0$ par $0$ jaate hain; $p > L$ ke saath flip-chip floor $0$ hai, jabki wire bonding abhi bhi $2$ edge pads fit karta hai — phir se woh small-geometry regime jahan perimeter area ko beat karta hai. Cell A ke saath consistent.

Ex 5 — Cell E: limiting case $p \to 0$

Worked example

Formulas kehti hain $N_{flip} = (L / p)^{2} \to \infty$ jab $p \to 0$ . Kya infinite I/O really hoti hai? Physics usse kahan rokti hai?

Forecast: Guess karo ki wall lithography, solder-ball physics, ya heat set karti hai.

Step 1. Mathematically, $L = 10 mm$ fix karo aur $p$ shrink karo: $p = 0.1$ par $N = 10, 000$ ; $p = 0.01$ par $N = 1, 000, 000$ . Ye step kyun? Pitch half karne se count chaar guna ho jaati hai — $1/ p^{2}$ term explode karta hai. Paper par koi limit nahi.

Step 2. Physical wall #1 — bump collapse & bridging. Solder bumps ki minimum diameter hoti hai; do bumps ek-doosre se ~diameter se kam door honge toh reflow mein ek ho jaate hain, neighbours short kar dete hain. Ye step kyun? Short ek electrical failure hai, connection nahi — isliye $p$ roughly bump size se neeche nahi ja sakta.

Step 3. Physical wall #2 — CTE stress. Tighter, chote bumps die aur board ke alag expand hone par har bump par zyada shear carry karte hain; ek pitch se neeche ye underfill ke saath bhi crack ho jaate hain. Ye step kyun? Limit ko ek reliability failure mode se connect karta hai, sirf geometry se nahi.

Step 4. Physical wall #3 — routing & signal integrity. Agar bumps fit bhi ho jayein, substrate ko woh hazaron nets bahar fan karne padte hain; escape routing layers khatam ho jaati hain. Ye step kyun? Bottleneck die face se package mein shift ho jaata hai, isliye pitch mass production mein ~0.1 mm par practically cap ho jaata hai.

Verify: $N (p = 0.1) = (10/0.1)^{2} = 10, 000$ ✓ aur $N (p = 0.01) = (10/0.01)^{2} = 1, 000, 000$ ✓. Math limit $\infty$ hai; engineering limit finite hai aur upar ke teen walls mein se smallest set karta hai.

Ex 6 — Cell F: real-world product decision

Worked example

Tum package kar rahe ho (a) ek sasta 8-pin temperature sensor die, $L = 1.2 mm$ , aur (b) ek 1500-I/O GPU die, $L = 15 mm$ , dono ek available pitch $p = 0.3 mm$ par. Har ek ke liye kaun sa method, aur kyun?

Forecast: Compute karne se pehle predict karo — 8-pin part ko kya area array ki zaroorat bhi hai?

Step 1. Sensor required I/O = 8. Wire-bond capacity: $⌊ 1.2/0.3 ⌋ = 4$ pads/edge, toh $4 \times 4 = 16 \geq 8$ . ✓ Ye step kyun? Demand (8) ko supply (16) se compare karo. Sasta perimeter method already room to spare rakhta hai.

Step 2. Sensor flip-chip capacity: $⌊ 1.2/0.3 ⌋^{2} = 4^{2} = 16$ . Yeh bhi enough hai — lekin flip-chip bumping + post-dicing underfill cost add karta hai koi benefit nahi 8 pins par. → Wire bonding choose karo. Ye step kyun? Jab dono methods requirement clear kar lein, sasta wala choose karo (parent note ki "superior ≠ cost-effective" mistake).

Step 3. GPU required I/O = 1500. Wire-bond capacity: $4 \times ⌊ 15/0.3 ⌋ = 4 \times 50 = 200$ . $200 < 1500$ ✗ — impossible. Ye step kyun? Edge simply 1500 pads hold nahi kar sakti; yeh wire bonding ko turant rule out karta hai.

Step 4. GPU flip-chip capacity: $⌊ 15/0.3 ⌋^{2} = 5 0^{2} = 2500 \geq 1500$ . ✓ → Flip-chip choose karo, jo ek hot GPU ke liye back-side heat-sink path bhi deta hai. Ye step kyun? Sirf area array pin count meet karta hai, aur yeh cooling bhi bonus-solve karta hai.

Verify: Sensor: $16 \geq 8$ (wire OK), $16 \geq 8$ (flip OK) → cost decide karta hai → wire bonding. GPU: $200 < 1500$ (wire fail), $2500 \geq 1500$ (flip works) → flip-chip. Dono decisions ek single inequality se follow karte hain.

Ex 7 — Cell G: ground bounce with signs and units

Worked example

Ek supply net $d i / d t = 0.5 A/ns$ se switch karta hai. Ek wire bond ( $L = 2 nH$ ) aur ek flip-chip bump ( $L = 0.05 nH$ ) ke liye voltage droop compute karo. Agar logic $1 V$ par run kare, kaun survive karta hai?

Forecast: Guess karo ki 2 nH wire kitne volts droop karta hai — kya yeh 1 V rail ko kharab kar dega?

Step 1. Units cleanly convert karo: $d i / d t = 0.5 A/ns = 0.5/1 0^{- 9} = 5 \times 1 0^{8} A/s$ . Ye step kyun? $V = L \frac{d i}{d t}$ ko SI chahiye: henries aur amps-per-second, toh hum "nano" clear karte hain.

Step 2. Wire: $V = L \frac{d i}{d t} = (2 \times 1 0^{- 9}) (5 \times 1 0^{8}) = 1.0 V$ . Ye step kyun? Faraday's law: inductance $L$ se changing current ek voltage banata hai jo change ko oppose karta hai (sign kehta hai yeh supply se ladhta hai, yaani ek droop).

Step 3. Bump: $V = (0.05 \times 1 0^{- 9}) (5 \times 1 0^{8}) = 0.025 V$ . Ye step kyun? Same law, 40× chota inductance → 40× chota droop.

Step 4. $1 V$ rail se compare karo: wire ka $1.0 V$ droop supply ka 100% hai — logic collapse ho jaata hai. Bump ka $0.025 V$ $2.5%$ hai — safe hai. Ye step kyun? Yeh parent note ka concrete "electrical reason flip-chip jeet ta hai" hai.

Verify: Units: $H \cdot A/s = (V \cdot s/A) (A/s) = V$ ✓. Droops ka ratio $1.0/0.025 = 40$ = inductances ka ratio $2/0.05 = 40$ ✓.

Ex 8 — Cell H: exam twist — rectangular die with mixed pitch

Worked example

Twist: die square nahi hai — yeh $L_{x} = 12 mm$ by $L_{y} = 6 mm$ hai. Aur bhi bura, pitch direction se alag hai: bumps $x$ -edges par $p_{x} = 0.2 mm$ par hain lekin $y$ -edges par $p_{y} = 0.3 mm$ par (yeh ek real constraint hai jab ek axis routing-limited ho). Wire-bond pitch bhi matching edges par same $p_{x}, p_{y}$ hai. Dono counts derive aur compute karo.

Forecast: Predict karo ki kaun sa square formula $2 (L_{x} + L_{y})$ gain karta hai aur kaun sa do alag ratios ka product gain karta hai — aur kya mixed pitch help karta hai ya hurt karta hai.

Step 1. Mixed pitch ke saath rectangle par wire bonding: do $x$ -length edges pitch $p_{x}$ use karti hain, do $y$ -length edges pitch $p_{y}$ use karti hain. Toh $N_{wire} = 2 ⌊ \frac{L _{x}}{p _{x}} ⌋ + 2 ⌊ \frac{L _{y}}{p _{y}} ⌋ .$ Ye step kyun? Wire bonding ek perimeter (1-D) resource hai; opposite edges ke har pair ko apna pitch milta hai. Do edges length $L_{x}$ ki hain (pitch $p_{x}$ ) aur do length $L_{y}$ ki (pitch $p_{y}$ ).

Step 2. Mixed pitch ke saath rectangle par flip-chip: face ek grid hai jisme $⌊ L_{x} / p_{x} ⌋$ columns aur $⌊ L_{y} / p_{y} ⌋$ rows hain, toh $N_{flip} = ⌊ \frac{L _{x}}{p _{x}} ⌋ \cdot ⌊ \frac{L _{y}}{p _{y}} ⌋ .$ Ye step kyun? Flip-chip ek area (2-D) resource hai; do axis pitches multiply hoti hain, square nahi, kyunki ab ye differ karte hain.

Step 3. Floors compute karo: $⌊ 12/0.2 ⌋ = ⌊ 60 ⌋ = 60$ aur $⌊ 6/0.3 ⌋ = ⌊ 20 ⌋ = 20$ . Ye step kyun? Dono ratios yahan whole numbers aate hain, toh floor kuch nahi badalta — lekin hum aadat se apply karte hain.

Step 4. Wire: $N_{wire} = 2 (60) + 2 (20) = 120 + 40 = 160$ . Ye step kyun? Dono floors ko perimeter formula mein plug karo.

Step 5. Flip-chip: $N_{flip} = 60 \times 20 = 1200$ . Ye step kyun? Dono floors ko area formula mein plug karo — do direction counts ka product.

Step 6. Sanity — simple cases mein reduce karo. $p_{x} = p_{y} = p$ aur $L_{x} = L_{y} = L$ set karo: toh $N_{wire} = 2 (2 L / p) = 4 L / p$ aur $N_{flip} = (L / p) (L / p) = (L / p)^{2}$ — exactly parent-note square formulas. ✓ Ye step kyun? Ek acchi generalisation special case mein collapse back honi chahiye; yeh prove karta hai ki humne kuch tora nahi.

Verify: $2 (60) + 2 (20) = 160$ ✓; $60 \times 20 = 1200$ ✓. Flip-chip yahan wire bonding ko $1200/160 = 7.5 \times$ beat karta hai, aur square-die reduction check pass karta hai. Note karo mixed pitch ne $y$ -axis density ko hurt kiya (coarser $0.3$ mm), isliye flip-chip ratio $7.5 \times$ hai, na ki $10 \times$ jo uniform $0.2$ mm par hota.

Active Recall

Recall Sirf 3 pitches wide die ke liye kaun sa cell jeetta hai, aur kyun?

Cell A → wire bonding. $L / p = 3$ ke saath, perimeter $4 \times 3 = 12$ , area $3^{2} = 9$ ko beat karta hai; ek chote number ko square karna use 4 se multiply karne se haarta hai.

Recall Exact square-die crossover kya hai, aur doosra root kahan se aata hai?

$L = 4 p$ . $x^{2} = 4 x$ solve karne par $x (x - 4) = 0$ milta hai, toh $x = 0$ (degenerate zero-width die) ya $x = 4$ (real crossover).

Recall Floor rule

$⌊ L / p ⌋$ kya enforce karta hai, aur yeh kab matter karta hai? Yeh integer number of pads force karta hai (koi partial site nahi). Yeh tab matter karta hai jab $L / p$ whole number na ho — jaise $⌊ 133.3 ⌋ = 133$ , ya $⌊ 0.5 ⌋ = 0$ (ek bhi bump fit nahi hota).

Recall Rectangular die with mixed pitch ke liye

$4 L / p$ aur $(L / p)^{2}$ ki jagah kya aata hai? $N_{wire} = 2 ⌊ L_{x} / p_{x} ⌋ + 2 ⌊ L_{y} / p_{y} ⌋$ (real perimeter) aur $N_{flip} = ⌊ L_{x} / p_{x} ⌋ \cdot ⌊ L_{y} / p_{y} ⌋$ (real area); dono square forms mein reduce ho jaate hain jab $L_{x} = L_{y}$ aur $p_{x} = p_{y}$ .

Recall

$p \to 0$ se infinite I/O kyun nahi mil sakti? Bump collapse/bridging, CTE shear cracking, aur substrate escape-routing sab practical pitch ko ~ $0.1$ mm ke paas cap kar dete hain.