KYA: hum transistor ko flat rakhke potential ko uske upar ek curve ki tarah draw karte hain.
KYUN: poori "leakage" kahani is curve ki shape ke baare mein hai — ek smooth valley matlab transistor off hai; ek sagging valley matlab drain ne chori se cross kar liya.
PICTURE (kya dhundho): laal curve ψ(x) ek kale rectangle (channel) ke upar draw hai. Beech mein ek valley mein dip karti hai; dono ends source (x=0, left) aur drain (x=Lg, right) par pinned hain. Ek kala arrow gate ko valley floor ko neeche dabaate hue dikhata hai. Gaur karo: gehra valley floor = electrons cross nahi kar sakte = transistor OFF.
KYA: hum ψ ko centre line par uski value aur ek gentle y2 bulge ke roop mein likhte hain.
KYUN: ek parabola sabse simple curve hai jo (a) beech mein flat ho sake aur (b) dono surfaces par gate ke zariye kheenchi ja sake — bilkul wahi physical picture.
PICTURE (kya dhundho): sheet ke through ek vertical cut, y page mein upar (top y=+tsi/2, bottom y=−tsi/2, centre y=0 dotted). Laal curve ψ vs y hai: centre par sabse flat (ψ0, labelled), dono gate-controlled surfaces ki taraf bahar bulge karta hai (dashed kali lines). Gaur karo: poori body ka potential ek centre value aur ek bulge se capture ho jaata hai.
KYA: hum demand karte hain ki field lines oxide cross karte waqt continuous rahen — silicon surface se nikalti field, gate ke oxide ke across lagayi field ke barabar ho.
KYUN: yahan gate ki authority maths mein enter hoti hai. Iske bina, channel gate ko feel hi nahi karta.
PICTURE (kya dhundho): teen stacked kale boxes — GATE (top), oxide thickness tox ka (beech mein, labelled), silicon body (bottom). Laal arrows gate se oxide ke through silicon mein neeche shoot karte hain: woh field lines hain jo boundary condition match karta hai. Gaur karo: oxide box ko chota karo aur same voltage drop zyada steep (stronger) arrows banata hai = tighter control.
KYA: algebra y ko eliminate karta hai; hum ek 1-D differential equation mein ψ0(x) ke liye reh jaate hain.
KYUN: ek 1-D equation actually solve karne layak hai aur usse ek length padhi ja sakti hai — parabola ki bet ka payoff.
PICTURE (kya dhundho): left par, small kale neeche arrows ka ek grid = body ke andar 2-D field map. Ek kala "reduce" arrow right ki taraf point karta hai ek single laal curve ψ0(x) par. Gaur karo: 2-D detail ek along-channel curve mein summarise ho gayi jiska curvature constants ka ek lump hai — woh lump 1/λ2 hai.
KYA: hum shifted equation solve karte hain aur physical branch select karte hain; drain ki intrusion ϕ=ϕDe−x/λ hai (long channel) ya ek non-decaying cosh-type profile (short channel).
KYUN: ab "drain kitni door tak pahunchta hai?" ka ek clear jawab hai — lagbhag λ. Lg≳5λ chahiye taaki mid-channel mein intrusion almost nothing ho.
PICTURE (kya dhundho): same channel ke upar do potential curves — ek kali long-channel curve (drain dip fade hoti hai, valley floor gehri rehti hai = OFF holds) aur ek laal short-channel curve (dono end-dips overlap karti hain, valley floor lift hota hai = leaks). Ek laal arrow fade distance λ label karta hai. Gaur karo: same λ, lekin jab Lg sirf kuch λ hai toh exponential tails nahi mare → leakage.
KYA: Step 3 ko 1, phir 3, phir 4 gated surfaces ke liye repeat karo aur terms add karo.
KYUN: yeh poore GAA idea ka payoff line hai — literally kyun channel ko wrap karna help karta hai, ek equation mein ek term ke roop mein.
PICTURE (kya dhundho): teen square cross-sections side by side — planar (sirf bottom edge laal), FinFET (top + two side edges laal = 3), GAA nanosheet (saari char edges laal = 4). Gaur karo: laal edges gino = pull-back terms gino; zyada laal = chhotaa reach λ.
PICTURE (kya dhundho):λGAA (laal) body size dsi ke against plot ki gayi — dsi=0 ke paas nearly flat aur small, phir bade dsi ke liye kale dashed asymptote dsi/4 hug karne ke liye badhti hai. Do labelled arrows thin-body (best) aur fat-body (planar-like) regimes mark karte hain.
YEH final figure kya karta hai: yeh poori chain ek line par rakhta hai — Poisson's law → parabola bet → gate boundary → 1-D equation jo λ paida karta hai → exponential decay → 1/Nsides gate-count win. Ise Steps 1–6 ke recap ke roop mein left se right padho, laal final box (gate-count payoff) ke saath jo punchline hai: zyada gated sides → chhotaa λ → chhotaa Lg bina leaking ke. Neeche har box exactly ek step se correspond karta hai jise tum abhi work through kar chuke ho.
PICTURE (kya dhundho): chhe small boxes kale arrows se left-to-right joined, ek per step; sirf aakhri box ("N sides, 1/sqrt(N)") laal hai, aur neeche ek laal caption punchline state karta hai. Flow dekho: charge law in, gate-count payoff out.
Channel ko ek valley imagine karo aur potential ko usmein paani ke level ki tarah, door ke calm bulk silicon se measure kiya gaya. Pehle hum conventions fix karte hain: bache hue dopant charge negative hai, aur y body ke across upar point karta hai. Gate valley floor ko neeche dabaata hai taaki woh sukha rahe (transistor OFF). Drain, door ke end par, ek reservoir hai jo cross karne ki koshish karta hai. Poisson's equation woh rulebook hai jo "charge kaise baitta hai" ko "valley kaisi dikhti hai" se jodta hai (Step 1) — aur kyunki thin body fully depleted hai, charge sirf ek fixed constant hai. Ise solve karne ke liye hum bet lagate hain ki potential thin body ke across ek simple parabola ki tarah muda hai (Step 2), phir hum gate ko bolne dete hain oxide ke across field lines match karke — thinner oxide, mazbooti se dabana — aur note karte hain ki top aur bottom oxides alag ho sakte hain (Step 3). Algebra poori tarah karte hue (tsi2/4 term rakho aur phir judge karo kab woh small hai), parabola ki across-body curvature ek restoring pull(ψ0−ψgate)/λ2 ban jaati hai, aur sab kuch channel ke saath ek equation mein fold ho jaata hai jiska single mystery constant ek length λ kehlaata hai (Step 4). Bacha hua dopant constant equilibrium se measure karke sweep ho jaata hai, saaf ϕ′′=ϕ/λ2 chhodke; uske paas ek growing aur ek decaying branch hai, aur physics (drain se door equilibrium par relax karo) growing wale ko throw away karta hai, toh drain ka flood exponentially fade hota hai distance ke saath, aur λ exactly woh hai kitni door tak pahunchta hai — toh channel ko 5λ lambe ki zaroorat hai taaki sukha rahe (Step 5). Finally, har extra gated side ek aur press add karta hai, apna term sum mein, denominator mein stack karke taaki λ1/Nsides ki tarah shrink kare (Step 6). Planar mein ek side hai, FinFET mein teen, GAA mein saari char — sabse chhotaa reach, sabse tight valley, sabse kam leak. Aur edge cases sahi behave karte hain: thin body → tiny λ, fat body → λ≈dsi/4 planar ki taraf wapas creep karta hai (Step 7). Woh aakhri line hi trade-off knob hai aur isi liye GAA nanosheets exist karte hain.
Recall Quick self-test
λ kaun si physical quantity measure karta hai? ::: Woh distance jitni door drain ka field channel mein penetrate (screen into) karta hai; drain disturbance e−x/λ ki tarah decay karta hai.
Zyada gate coverage λ kyun chhotaa karta hai? ::: Har gated surface 1/λ2 sum mein ek pull-back term add karti hai, toh identical faces ke liye λ∝1/Nsides.
Constant dopant source kahan jaata hai jab hum ϕ′′=ϕ/λ2 tak pahunchte hain? ::: Yeh variable shift karke absorb ho jaata hai (far-from-drain equilibrium se measure karke); yeh set karta hai ki "flat" kahan hai, reach λ nahi.
Do branches mein se decaying exponential kaise choose karte hain? ::: x=0 drain par rakho aur demand karo ki ϕ→0 ek long channel mein gehraai mein; growing branch wahan blow up karta hai, toh uska coefficient zero hona chahiye, ϕ=ϕDe−x/λ bachta hai.
Fat-body limit mein λGAA kya hai? ::: λGAA→dsi/4, planar-jaisi poor control ki taraf wapas drift — drive-vs-control trade-off.
Lg≳5λ kyun zaroori hai? ::: Taaki exponentially decaying drain intrusion mid-channel tak almost zero ho jaaye, OFF valley ko gehri rakhte hue.
Related: Subthreshold slope and gate electrostatics · Epitaxy and SiGe superlattices · CFET (complementary FET) · back to the parent topic.