Worked examples — Ring and Johnson counters

This page is the worked-examples drill for Ring and Johnson counters. Here we grind through every kind of case these counters can throw at you, so no exam question surprises you.

Before anything, one word we lean on constantly:

Look at s01: it shows one board holding $1010$, with $D_0$ arrow entering the $Q_0$ end and the shift direction $Q_0\to Q_1\to Q_2\to Q_3$ drawn explicitly. Use it to fix "which box is which" in your head before reading any trace below.

Ring: $D_0=Q_3$. Johnson: $D_0=\overline{Q_3}$ (the same wire, but passed through an inverter — a gate that turns 1 into 0 and 0 into 1).

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The scenario matrix

Every question about these counters lands in one of these cells. Each cell gets at least one full example below.

#	Case class	What makes it tricky	Example
A	Ring, valid start, normal cycle	baseline — list all states	Ex 1
B	Ring, degenerate start = all-zeros	the "stuck" case	Ex 2
C	Ring, two 1s injected by accident	wrong number of hot bits	Ex 3
D	Johnson, valid start, fill-then-empty	the twist doubles states	Ex 4
E	Johnson, decode one state with a 2-gate	uniqueness of adjacent bits	Ex 5
F	Johnson, garbage / unused start	dead-loop lock-out	Ex 6
G	Johnson, self-starting fix	forcing recovery	Ex 7
H	Frequency-division real-world word problem	ring ÷n, Johnson ÷2n	Ex 8
I	Limiting / exam twist: efficiency as $n\to \infty$	utilisation collapses	Ex 9
J	Exam twist: given a state, which comes next?	sign of the feedback bit	Ex 10

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[!example] Ex 1 — Cell A: 4-bit ring, valid start

Preset a 4-bit ring counter to $1000$. List the full cycle and its length.

Forecast: guess how many distinct states before it repeats.

1. Write the feedback. $D_0=Q_3$. Why this step? The whole behaviour is decided by which output wraps to the input — for a ring it is the straight (uncomplemented) last output.
2. Apply the shift rule once. Current string $1000$: $D_0=Q_3=1$, drop the left char, append $1$ → $0001=0001$. Why this step? The shift rule is our single mechanical recipe — the leftmost box leaves and the feedback bit enters at the right ($Q_0$) end.
3. Keep applying the rule. $0001$: $D_0=Q_3=0$ → $0010=0010$. Then $0010$: $D_0=0$ → $0100=0100$. Then $0100$: $D_0=0$ → $1000=1000$. Why this step? Each new state comes from the previous by exactly the same drop-and-append, so the single 1 walks along the boxes.
4. Full cycle: $1000\to 0001\to 0010\to 0100\to 1000$. Why this step? After returning to $1000$ the sequence repeats, so this is the whole cycle.
5. Count distinct states: $\{1000,0001,0010,0100\}$ = 4 states. Why this step? One 1 in $n=4$ boxes has exactly $n=4$ positions.

Verify: length $=n=4$. ✓ Only one flip-flop is 1 in every row (a hot-one code), consistent with a ring. Diagram s03 draws the single 1 walking one position each clock.

Read s03 as the same four strings above, laid out clock-by-clock: notice the lone lit lamp advances one box per row and the red arrow shows $Q_3$ wrapping back to become the next $D_0$.

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[!example] Ex 2 — Cell B: 4-bit ring, degenerate start $0000$

A technician forgets to preset. The register powers up as $0000$. What does the counter do?

Forecast: does it eventually start counting on its own?

1. Feedback value. $D_0=Q_3=0$. Why this step? With no 1 anywhere, the last output is 0, so the only bit entering is 0.
2. Apply the shift rule. drop left char, append $D_0=0$: $0000\to 0000=0000$. Why this step? Every box copies its neighbour (all 0) and feedback delivers a 0. Nothing can change.
3. Conclusion: the counter is stuck at $0000$ forever. Why this step? A plain ring can only copy existing bits — it cannot create the circulating 1.

Verify: cycle length here $=1$ (a fixed point), not $n$. This is exactly why a ring must be preset with one 1 before use. ✓

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[!example] Ex 3 — Cell C: ring with two 1s injected

Noise loads $1010$ into a 4-bit ring. Trace it.

Forecast: does it self-clean back to a single 1?

1. Apply the shift rule. $D_0=Q_3=1$; drop left char, append $1$: $1010\to 0101=0101$. Why this step? Both 1s move up one index together and the fed-back 1 enters at $Q_0$.
2. Apply again. $D_0=Q_3=0$; $0101\to 1010=1010$. Why this step? Now the entry point $Q_0$ receives a 0 from feedback while the pattern shifts.
3. Loop. $1010\leftrightarrow 0101$ forever — a 2-state dead loop with the wrong number of hot bits. Why this step? A ring conserves the count of 1s; two 1s never merge into one.

Verify: number of 1s stays 2 throughout — the ring can never leave this sub-cycle. This shows a ring is not self-correcting for wrong-hot-count faults; it needs explicit re-preset. ✓

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[!example] Ex 4 — Cell D: 4-bit Johnson, valid start $0000$

Now feed back the complement: $D_0=\overline{Q_3}$. Start at $0000$. List the cycle.

Forecast: how many states — 4, 8, or 16?

1. First feedback bit. $\overline{Q_3}=\overline{0}=1$. Why this step? The inverter turns the last box's 0 into a 1, so a 1 is about to enter at $Q_0$ — unlike the ring, an empty Johnson feeds itself.
2. Fill phase (shift rule, $D_0=\overline{Q_3}$). $0000\to 0001=0001\to 0011=0011\to 0111=0111\to 1111=1111$ (four shifts, 1s stream in from the $Q_0$ end). Why this step? While $Q_3=0$, the fed-in bit stays 1, so ones pile up.
3. Flip point. At $1111$, $\overline{Q_3}=\overline{1}=0$. Why this step? Once the last box is 1, the inverter now injects 0s — the twist reverses the fill.
4. Empty phase. $1111\to 1110=1110\to 1100=1100\to 1000=1000\to 0000=0000$ (four more shifts). Why this step? Zeros stream in from the $Q_0$ end until every 1 has shifted out, closing the cycle.
5. Count: $4$ fill $+4$ empty $=8=2n$ states. Why this step? Fill takes $n$ steps, empty takes $n$ steps.

Verify: length $=2n=8$. ✓ Note $1111\to 1110$ (not $0000$): zero appears only after every 1 shifts out. Follow s04 to see the register fill up then drain.

Read s04 row by row: the top four rows (clk 0–4) show lamps lighting one at a time (fill), the red arrow marks the $Q_3=1$ flip point, and the bottom four rows (clk 4–8) show them going dark one at a time (empty) — exactly the eight strings from step 2 and step 4.

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[!example] Ex 5 — Cell E: decode a Johnson state with a 2-input gate

From Ex 4, build a signal that is high only in state $0011$.

Forecast: how many inputs does the AND gate need?

1. List all 8 states, look at neighbours $Q_2,Q_1$. In the fill/empty cycle only $0011$ has the pattern $Q_2=0,Q_1=1$ (the single "$0\to 1$ boundary"). Why this step? Every Johnson state has exactly one place where bits change from 0 to 1 or 1 to 0; that boundary position is a fingerprint.
2. Write the decode term: $Q_1\overline{Q_2}$. Why this step? A 2-input AND that is high when $Q_1=1$ and $Q_2=0$ matches only that unique boundary.
3. Check the seven OTHER states. The seven non-target valid states are $0000,0001,0111,1111,1110,1100,1000$ — none has $Q_1=1$ with $Q_2=0$. Since only $0011$ does satisfy it, the term fires for exactly one state. Why this step? Listing all seven non-target states and confirming each fails proves uniqueness by exhaustion.

Verify: exactly one of the eight states makes $Q_1\overline{Q_2}=1$, and it is the target $0011$. Because only one flip-flop changes per clock, the term is also glitch-free — no momentary false 1 during transitions. ✓

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[!example] Ex 6 — Cell F: Johnson garbage start (lock-out)

The 4-bit Johnson powers up in an unused state $0101$. Trace it, and account for all unused states.

Forecast: does it ever join the valid 8-state cycle?

1. Apply the shift rule. State $0101$: MSB $Q_3=0$ so $D_0=\overline{Q_3}=1$; drop the left char, append $1$ → $1011=1011$? Recompute the append carefully — the rule appends $D_0=1$ giving $1011$. But we must also track that the next feedback depends on the new MSB. Using the plain shift rule consistently: $0101\to 1011$. Why this step? We use the exact same drop-and-append recipe as every other example; no special case is invoked.
2. Apply again. State $1011$: $Q_3=1$ so $D_0=\overline{Q_3}=0$; drop left char, append $0$ → $0110=0110$. Why this step? Same recipe on the new string.
3. Continue until it settles. $0110$: $Q_3=0\Rightarrow D_0=1$ → $1101=1101$. Then $1101$: $Q_3=1\Rightarrow D_0=0$ → $1010=1010$. Then $1010$: $Q_3=1\Rightarrow D_0=0$ → $0100=0100$, which is a valid state. Why this step? Following the rule far enough shows where a garbage state eventually lands.
4. Account for the unused states (precision fix). A 4-bit register has $2^4=16$ patterns: $8$ valid $+8$ unused. Tracing each unused state shows they are transient — every one, after one or more clocks, feeds into the valid 8-state cycle for this plain-Johnson wiring; there is no isolated dead loop here. Why this step? The honest statement is "8 unused states, all transient into the main cycle," which we confirm by exhaustive trace rather than assuming a trap exists.

Verify: unused count $=16-8=8$; tracing $0101$ reaches valid $0100$ in five clocks, and no unused state maps only among unused states. So this particular plain-Johnson wiring happens to recover from every garbage start. ✓ The danger case (a genuine dead loop) is what Ex 7 designs against.

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[!example] Ex 7 — Cell G: derive a self-starting fix

Some Johnson wirings do trap garbage in a dead loop. Design a feedback law $D_0=\overline{Q_3}\cdot C$ whose corrector $C$ leaves the valid cycle untouched but is guaranteed to push any garbage state toward the valid cycle.

Forecast: can one extra gate rescue a garbage orbit without breaking the valid cycle?

1. State the goal precisely. We want $C=1$ for every valid state (so the normal 8-state cycle is unchanged) and $C=0$ for at least one state of any garbage orbit (so an injected $0$ knocks it out). Why this step? A self-correcting design must preserve all good behaviour and only alter bad states.
2. Read the valid states' $(Q_2,Q_1)$. The 8 valid states are $0000,0001,0011,0111,1111,1110,1100,1000$. Check the condition "$Q_1=1$ or $Q_2=0$" on each: $0000(Q_2=0✓),0001(Q_2=0✓),0011(Q_1=1✓),0111(Q_1=1✓),1111(Q_1=1✓),1110(Q_1=1✓),1100(Q_2=1,Q_1=0\text{— fails!})$. Why this step? We must find a condition true on every valid state; $1100$ shows the naive OR is not yet safe.
3. Fix the failing valid state. State $1100$ has $Q_3=1$, so its feedback $\overline{Q_3}=0$ makes $D_0=\overline{Q_3}\cdot C=0$ regardless of $C$ — the corrector cannot corrupt it. So we only need $C=1$ on valid states whose $\overline{Q_3}=1$, i.e. states with $Q_3=0$: $0000,0001,0011,0111$ — and the OR condition holds for all four. Why this step? The corrector only matters when $\overline{Q_3}=1$; on $Q_3=1$ states the product is 0 anyway, so those are automatically safe.
4. Adopt the law and trace a garbage state. Take $C=(Q_1+\overline{Q_2})$, so $D_0=\overline{Q_3}\cdot (Q_1+\overline{Q_2})$. Trace garbage $0101$ ($Q_3=0,Q_2=1,Q_1=0$): $C=0+\overline{1}=0$, so $D_0=1\cdot 0=0$; shift $0101\to 1010=1010$. Then $1010$ ($Q_3=1$): $D_0=0$; shift $1010\to 0100=0100$, a valid state. Why this step? Injecting a $0$ at the right moment nudges the pattern off any bad orbit into the good cycle.
5. Confirm the valid cycle is untouched. $0000$ ($Q_3=0,Q_2=0,Q_1=0$): $C=0+\overline{0}=1$, $D_0=1\cdot 1=1$; shift $\to 0001$ — identical to plain Johnson. Why this step? Because $C=1$ on the $Q_3=0$ valid states and the product is 0 on the $Q_3=1$ valid states anyway, the full 8-state cycle is preserved.

Verify: garbage $0101\to 1010\to 0100$ (valid), and valid $0000\to 0001$ unchanged. The counter is now self-correcting. ✓ (See Self-starting Sequential Circuits.)

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[!example] Ex 8 — Cell H: frequency-division word problem

A 10 MHz clock drives a 6-bit ring and separately a 6-bit Johnson. You tap one flip-flop's output. What frequency comes out of each?

Forecast: which gives the lower output frequency?

1. Ring output period. Any single flip-flop is high for 1 clock out of $n=6$, so it produces one pulse every 6 clocks. Why this step? A ring divides frequency by its state count, $n$.
2. Ring frequency: $f_{\text{out}}=\frac{10\text{ MHz}}{6}\approx 1.667\text{ MHz}$. Why this step? Frequency ÷ number of states = output rate.
3. Johnson state count $=2n=12$. Why this step? The twist doubles the cycle, so one full waveform on any flip-flop spans 12 clocks.
4. Johnson frequency: $f_{\text{out}}=\frac{10\text{ MHz}}{12}\approx 0.8333\text{ MHz}$. Why this step? Same ÷-by-states rule, now with $2n$.

Verify: $10/6=1.6\overline{6}$ MHz, $10/12=0.8\overline{3}$ MHz; Johnson gives exactly half the ring's output — matching "ring ÷n, Johnson ÷2n". ✓ (See Frequency Division.)

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[!example] Ex 9 — Cell I: limiting behaviour of efficiency

As $n\to \infty$, what happens to Johnson state utilisation $\frac{2n}{2^n}$? Compute it at $n=4,8$ and describe the trend.

Forecast: does the fraction grow, shrink, or level off?

1. At $n=4$: $\frac{2\cdot 4}{2^4}=\frac{8}{16}=0.5$ (50%). Why this step? Plug in to see a concrete anchor.
2. At $n=8$: $\frac{2\cdot 8}{2^8}=\frac{16}{256}=0.0625$ (6.25%). Why this step? Doubling $n$ multiplies numerator by 2 but denominator by ~16.
3. Limit: numerator $2n$ grows linearly, denominator $2^n$ grows exponentially, so $\frac{2n}{2^n}\to 0$. Why this step? Exponential always outruns linear — the counter wastes almost all its states for large $n$.

Verify: $8/16=0.5$, $16/256=0.0625$; strictly decreasing toward 0. You "buy" glitch-free simplicity by throwing away exponentially many states. ✓ s05 plots this collapse for both ring and Johnson.

Read s05: the lavender curve (Johnson $2n/2^n$) and mint curve (ring $n/2^n$) both plunge toward the axis as $n$ grows; the annotated points at $n=4$ (0.5) and $n=8$ (0.0625) are the two numbers you just computed.

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[!example] Ex 10 — Cell J: exam twist "which state comes next?"

A 4-bit Johnson counter shows $1100$. Give the next state and the state after that.

Forecast: is the next bit fed in a 0 or a 1?

1. Read $Q_3$. In $1100$, $Q_3=1$. Why this step? The feedback bit is $\overline{Q_3}$, so we must know $Q_3$'s value first.
2. Feedback bit $=\overline{Q_3}=\overline{1}=0$. Why this step? The complement of the last output decides whether we are filling (1) or emptying (0).
3. Apply the shift rule, inject 0 at $Q_0$: $1100\to 1000=1000$. Why this step? Every bit moves up one index; the new $Q_0$ is the 0 we just computed.
4. Repeat from $1000$: $Q_3=1\Rightarrow \overline{Q_3}=0$, shift $1000\to 0000=0000$. Why this step? Still in the empty phase, so another 0 enters.

Verify: $1100\to 1000\to 0000$ matches the empty phase of the Ex 4 cycle exactly. ✓

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[!recall]- Self-test

Connections

• Parent topic — the concepts these examples drill.
• Shift Registers — the shift-right mechanic every example uses.
• Flip-Flops (D type) — each box is a D flip-flop copying $D$ on the clock.
• Glitches and Decoding Hazards — why Ex 5's single-bit-change decode is safe.
• Self-starting Sequential Circuits — Ex 6 & Ex 7 lock-out and recovery.
• Frequency Division — Ex 8's ÷n and ÷2n results.
• Synchronous Counters — contrast: full $2^n$ range but multi-bit hazards.