Question bank — Ring and Johnson counters

False. A ring counter encodes the count as the position of one hot bit among $n$ cells, so there are exactly $n$ states — the $2^n$ figure belongs to a binary counter. On the figure's left ring, count the labelled nodes: only four.

True. It fills the register with 1s in $n$ steps, then empties it in $n$ steps, so the cycle length is $n+n=2n$. On the figure's right ring, trace the top-going arrows ($0000\to 0001\to \cdots \to 1111$, the fill) then the bottom-going arrows ($1111\to 1110\to \cdots \to 0000$, the empty): four plus four is eight.

False, and here is the step-by-step why. In a ring counter, feeding $Q_3$ back means "whatever leaves the end re-enters unchanged", so a single $1$ merely orbits $n$ positions — the state graph is one small loop of length $n$ (left ring in the figure). Insert the inverter so $\overline{Q_3}$ feeds back, and the rule becomes "whatever leaves re-enters flipped." Now, starting empty, a $1$ is injected each clock until the register is full ($n$ new states never visited before), and only then does the feedback flip to $0$ and inject zeros for another $n$ states. Those $2n$ states form one big loop (right ring). So one wire doesn't tweak the loop — it stitches a second half onto the state graph, exactly doubling $n\to 2n$ and giving each state a unique adjacent-bit boundary for 2-gate decoding. Fundamental, not cosmetic.

False. A ring counter must be preset with exactly one $1$, and a Johnson counter cleared to all-$0$; otherwise either can sit in a stuck or dead-loop state.

False. At $1111$ the feedback is $\overline{Q_3}=0$, so a single $0$ shifts in giving $1110$. All-zero appears only after all four 1s have shifted out — follow the arrow leaving the $1111$ node on the figure's right ring; it points to $1110$, not back to $0000$.

False, but for different reasons per counter. A Johnson counter changes exactly one flip-flop output per clock, so no two decoded-output gates can race — that is what makes it glitch-free. A ring counter actually toggles two flip-flop outputs per step (the hot bit vacates one cell and fills the next), yet it is still glitch-free because each state has a single lone $1$: the decoded output is just that one $Q$ line, needing no multi-input gate to race in the first place. Both avoid the binary counter's problem where many bits flip at once through combinational decode logic (see Glitches and Decoding Hazards).

Depends on your goal, not "worse". A ring counter divides the clock by $n$; a Johnson counter by $2n$. Same flip-flops, but Johnson gives twice the division ratio (see Frequency Division).

False. For the same state count, Johnson uses more flip-flops — its utilisation is $2n/2^n$, far below $1$. You pay silicon in exchange for glitch-free, decode-cheap operation.

False. Only 8 of the 16 patterns are valid; patterns like $0101$ or $1010$ are unused and can form a dead loop — you will not find $0101$ anywhere on the figure's right ring.

Error: that is a ring counter. A Johnson counter needs $D_0=\overline{Q_3}$ — the complemented last output.

Error: feedback only copies existing bits. With all cells $0$, $D_0=Q_3=0$ forever, so it stays $0000$. You must inject a $1$ via preset.

Error: each Johnson state has a unique adjacent-bit boundary (a single $0\to 1$ or $1\to 0$ edge), so a 2-input gate suffices — e.g. $Q_1\overline{Q_2}$ decodes $0011$.

Error: two flip-flops toggle here — $Q_3$ goes $1\to 0$ and $Q_2$ goes $0\to 1$. The "single-flip-flop-changes" glitch-free property belongs to the Johnson counter; a ring counter's hot bit moves, which flips two cells at once. What is single is the hot bit (one $1$ in the pattern), not the number of toggling outputs — trace this exact step as the first arrow on the figure's left ring.

Error: $Q_0{Q}_1$ is not unique — state $0111$ also has $Q_0=Q_1=1$. The unique boundary for $0011$ is $Q_1\overline{Q_2}$.

Error: the clock is untouched. Self-starting modifies the feedback logic so every unused state maps into the valid cycle (see Self-starting Sequential Circuits).

Because the register only shifts — each clock every cell copies its left neighbour, so a single $1$ moves as a block; nothing duplicates it.

Once the last stage becomes $1$, feedback flips to $0$ and starts injecting 0s; these 0s push through the same shift direction, emptying the register in the order the 1s entered.

The state is the count directly — the position of the hot bit (ring) or the fill-level (Johnson) is readable straight off the flip-flop outputs, no arithmetic decode needed.

It packs $2^n$ counts into $n$ bits, but reaching, say, $0111\to 1000$ flips four flip-flop outputs "simultaneously"; tiny timing differences make momentary wrong patterns (glitches on the decoded outputs). Johnson trades that density for a single flip-flop output changing per clock.

Because exactly one flip-flop output changes between adjacent states, a decode gate can never momentarily see a false transient pattern — the single-change property already removes the race, so no special hazard immunity has to be added.

Clearing gives $0000$, which is a stuck state for a ring counter (no $1$ to circulate). You must preset a lone $1$, or add feedback logic that regenerates one.

No — with no cells there is nothing to shift and no state, so both formulas ($N_{\text{ring}}=n$, $N_{\text{Johnson}}=2n$) give $0$. The domain of both designs is $n\ge 1$; $n=0$ is degenerate and excluded.

With $D_0=Q_0$, whatever bit you load just holds forever ($N_{\text{ring}}=n=1$) — a single degenerate "state", useless as a counter.

With $D_0=\overline{Q_0}$, the single bit toggles each clock: $0\to 1\to 0\dots$, giving $2n=2$ states — effectively a divide-by-2 (a toggle flip-flop).

It enters a dead loop of unused states never joining the main cycle; only self-starting feedback can rescue it. (The valid cycle is $0000,0001,0011,0111,1111,1110,1100,1000$ — $0100$ is not among the nodes on the figure's right ring.)

No — it is an unused state. It still shifts cleanly ($1100\to 0110\to 0011\to 1001\to 1100$), forming a 4-state dead loop parallel to the real cycle shown on the figure's left ring, so it counts but reports wrong values.

$8/2^8=8/256\approx 3\%$. It uses only 8 of 256 possible patterns — you buy simplicity and zero glitches with a lot of unused silicon.

$\overline{Q_3}=0$. The queued input has already flipped to $0$ even though the outputs are still all-$1$, which is why the next state begins the emptying phase.