2.5D packaging and interposers: Visual walkthrough

6.5.2 · D2 · Hardware › Advanced & Emerging Architectures › 2.5D packaging and interposers

Yeh 2.5D packaging and interposers ke liye companion visual derivation hai. Har symbol pehle kamaya jaata hai, phir use kiya jaata hai. Ek samajhdaar 12-saal-ka baccha bhi line one se follow kar sakta hai.

Step 1 — Ek wire electrically hoti kya hai?

YEH YAHAaN se KYUN shuru karein? Kyunki "kitni energy?" ya "kitni fast?" poochne se pehle hume yeh agree karna hoga ki energy kis physical cheez se lad rahi hai. Woh cheez hai capacitance.

PICTURE. Figure dekho. Neeli metal line wire hai; uske neeche latkti hui choti grey plates hain jo ground plane ke saath capacitance represent karti hain. Lambi wire = zyada choti plates parallel mein = badi bucket.

Step 2 — Capacitance length ke saath badhti hai

YEH STEP KYUN? Yeh woh akela fact hai jo geometry (wire kitni lambi hai) ko physics (woh kitna charge khaati hai) se jodta hai. Iske baad ki har cheez isi par tikhi hai.

PICTURE. Figure mein ek choti wire aur ek lambi wire side by side dikhti hain. Buckets gino: lambi wire (orange) mein zyada hain. Chote graph mein seedhi laal line dikhati hai ki $C$ , $L$ badhne ke saath seedhi line mein upar jaata hai — woh seedhapan hi "proportional" word hai.

Step 3 — Ek bit bhejne ki cost kya hai?

" $\frac{1}{2} C V^{2}$ " tool KYUN? Hume energy chahiye jo capacitor charge hone par stored hoti hai, kyunki energy-per-bit chip power budgets ki currency hai. Ek capacitor ko empty se voltage $V$ tak charge karne ka physics result exactly $\frac{1}{2} C V^{2}$ hai — koi aur formula yeh nahi batata ki "bucket bharne mein kitni energy lagi?".

Punchline: $c$ aur $V$ fixed rahen toh $E_{bi t}$ , $L$ ke directly proportional hai. Choti wire → sasta bit.

PICTURE. Figure mein bucket level $V$ tak bhari hui hai; shaded area stored energy hai. Shaded triangle notice karo — uski average height $V /2$ hai, jahan se $\frac{1}{2}$ aata hai.

Step 4 — Interposer vs PCB: real lengths daalo

Ek ratio KYUN compare karein? Kyunki absolute joules kuch messy constants par depend karte hain jo hum yaad nahi karna chahte. Ek ratio shared cheezein cancel kar deta hai aur lever saaf dikhata hai.

PICTURE. Dono routes scale mein draw kiye gaye hain: lamba looping PCB trace (grey) aur seedha chota interposer trace (blue), saath mein unke energy bars.

Step 5 — Doosra axis: parallel wires se bandwidth

Multiply KYUN, add kyun nahi? Har wire ek independent lane hai. Total throughput = lanes × per-lane rate — usi reason se jaisa ek 4-lane road same speed par 1-lane road se 4× zyada cars carry karta hai.

PICTURE. Figure mein kaafi saari wires stack ki gayi hain; har ek rate $f$ par bits tick karti hai; daayein taraf summed arrow total $B W$ hai.

Step 6 — "Pitch" $N_{w i r es}$ kaise decide karta hai

Pitch poora game KYUN hai. PCB pitch ~ $100 μ m$ hai; interposer pitch (chip-grade lithography, lithography frontier ke paas) ~ $1 μ m$ hai. Same edge, $100 \times$ zyada wires.

PICTURE. Upar same fixed edge width $W$ ; neeche fat-pitch PCB mein 4 wires fit hain, fine-pitch interposer mein bahut saari. Gino unhe.

Yehi exactly reason hai ki HBM ko interposer kyun chahiye: uska ~1024-bit bus hazaaron fine wires chahta hai jo koi PCB route nahi kar sakta.

Step 7 — Cost twin: yield vs die area

Exponential $e^{- D A}$ KYUN? Defects wafer par randomly girti hain. Agar area $A$ wale ek die par defects ki average sankhya $D A$ hai, toh zero defects milne ki probability Poisson rule follow karti hai: "0 events ki probability $= e^{- mean}$ ". Koi aur simple law yeh capture nahi karta ki "ek bura spot poori die ko barbad karta hai". Dekho Wafer Yield and Defect Density.

PICTURE. Curve $Y = e^{- D A}$ plot ki gayi hai; red dot $A = 4$ par (deep in the collapse), chaar green dots $A = 1$ par (healthy shoulder par upar).

Step 8 — Edge & degenerate cases (kabhi gap mat chhodna)

$L \to 0$ (chips touching): $E_{bi t} = \frac{1}{2} c L V^{2} \to 0$ . Zero-length wire mein zero charging energy lagti hai — ideal 2.5D limit. Real chiplets touch nahi kar sakte (microbumps chahiye), lekin interposer karib pahunchta hai.
$A \to 0$ (tiny die): $Y = e^{- D \cdot 0} = e^{0} = 1$ . Ek dust-speck die essentially hamesha acchi hoti hai — lekin thousands chahiye honge aur unke beech wiring explode kar jaati hai. Trade-off real hai, free lunch nahi.
$A \to \infty$ (giant die): $Y = e^{- D A} \to 0$ . Yield khatam ho jaati hai, aur pehle reticle limit hit ho jaati hai — monolithic path literally dead-end hai. Dekho Reticle Limit and Lithography.
$D \to 0$ (perfect fab): $Y \to 1$ kisi bhi area ke liye — agar koi defect hi na ho, toh bade dies theek rahenge aur yield argument khatam. Toh 2.5D ka cost case defects hone par depend karta hai. Yeh bandwidth/energy case (Steps 1–6) hai jo apne dam par khada hai.
$p \to \infty$ (huge pitch): $N_{w i r es} = W / p \to 0$ — koi wire fit nahi, koi bandwidth nahi. Yeh HBM ke liye PCB failure mode hai, exaggerated.

PICTURE. Chaar mini-plots ka ek small panel jo har limit dikhata hai: energy→0, yield→1, yield→0, wires→0.

Ek-picture summary

Is page ki har cheez do levers hain jo same direction mein pull karti hain, dono geometry shrink karne se improve hoti hain:

Length lever → choti wires → kam $E_{bi t} = \frac{1}{2} c L V^{2}$ .
Pitch lever → barik wires → zyada $N_{w i r es} = W / p$ → zyada $B W = N \times f$ .
Area lever → chote dies → zyada $Y = e^{- D A}$ .

Interposer length aur pitch levers pull karta hai; chiplets area lever pull karte hain. Saath milkar yeh monolithic die ko speed, energy, aur cost teeno par haraate hain.

Recall Feynman retelling — plain words mein wapas bolo

Ek wire ek bucket hai jise aapko charge se bharna padta hai tab jaake doosra end notice kare; lambi wire badi bucket hoti hai, toh zyada energy per bit lagti hai — yeh hai $E = \frac{1}{2} c L V^{2}$ , aur length $L$ villain hai. Interposer wire ko chota aur patla dono banata hai, toh energy mein jeetta hai. Yeh wires ko paas paas bhi banata hai (fine pitch), toh same edge ke saath-saath saikdon wires fit hoti hain, aur bandwidth sirf "wires times speed per wire" hai, $B W = N \times f$ — zyada wires, zyada bandwidth, isliye HBM ka 1024-bit bus sirf ek interposer par hi reh sakta hai. Alag se, bade single chips zyada baar mar jaati hain kyunki defects randomly girti hain aur ek bhi poori chip kharab karne ke liye kaafi hai: $Y = e^{- D A}$ area badhne par crash karta hai, toh hum chip ko chote chiplets mein kaatte hain jo akele bahut zyada baar survive karte hain. Har knob ko extreme tak push karo aur story kaaim rehti hai: zero length mein zero energy, zero area hamesha accha, infinite area kabhi kaam nahi karta. Interposer + chiplets = faster, sasta, aur actually manufacturable.

Recall Quick self-check

$E_{bi t} = \frac{1}{2} c L V^{2}$ mein kaunsa symbol interposer shrink karta hai? ::: $L$ (wire length) — aur yeh $c$ bhi kam karta hai. $B W = N \times f$ mein fine pitch kaise help karta hai? ::: Yeh $N$ badhata hai, kyunki $N = W / p$ aur chota $p$ same edge $W$ par zyada wires fit karta hai. $Y = e^{- D A}$ chiplets ko kyun favour karta hai? ::: Har die ka chota $A$ matlab exponent chota hai, toh $Y$ collapse hone ki bajaye 1 ke paas rehta hai. $L \to 0$ energy per bit ko kya karta hai? ::: $E_{bi t} \to 0$ drive karta hai — ideal short-wire limit.