Chiplets and multi-die integration: Worked examples

6.5.1 · D3 · Hardware › Advanced & Emerging Architectures › Chiplets and multi-die integration

Yeh page Chiplets and multi-die integration se yield aur energy ka math drill karti hai jab tak har case class routine na lag jaye. Pehle hum ek map banate hain har us scenario ka jo topic throw kar sakta hai, phir har cell ko work karte hain.

The scenario matrix

Kuch bhi work karne se pehle, yeh hai poori case classes ki list. Har worked example neeche us cell ke saath tagged hai jo woh fill karta hai.

Cell	Case class	Kya stress ho raha hai	Example
A	Baseline big monolith	$Y = e^{- D_{0} A}$ bade $A$ ke saath (yield near zero)	Ex 1
B	$N$ chiplets mein split	per-chiplet yield $e^{- D_{0} A / N}$	Ex 2
C	Degenerate: $A \to 0$ ya $D_{0} \to 0$	yield $\to 1$ (limiting value)	Ex 3
D	Degenerate split: $N = 1$	chiplet formula ko monolith reduce karna chahiye	Ex 3
E	Limit $N \to \infty$	per-chiplet yield $\to 1$ , lekin assembly cost explode karti hai	Ex 4
F	Energy: length half	$E_{bit} \propto L$ , change ka sign	Ex 5
G	Energy: off-package vs on-package	order-of-magnitude ratio (cm vs µm)	Ex 6
H	Real-world cost word problem	good-dies-per-wafer, cost per good die	Ex 7
I	Exam twist: $D_{0}$ ya $A$ solve karo	$ln$ se exponential invert karo	Ex 8
J	Break-even: chiplets kab jeetते hain?	total cost compare karo, crossover dhundho	Ex 9

Hum har cell A–J hit karenge.

Cell A — the doomed monolith

Worked example Ex 1 — Bada die, brutal yield

Ek monolithic die ka area $A = 750$ mm² hai ek aisi process par jiska defect density $D_{0} = 0.006$ defects/mm² hai. Yield kya hai?

Forecast: pehle guess karo — kya aadhe se zyada ya kam dies good honge? (Hint: exponent bada hoga.)

Step 1. Exponent form karo $D_{0} A = 0.006 \times 750 = 4.5$ . Yeh step kyun? Yield formula $Y = e^{- D_{0} A}$ sirf product $D_{0} A$ par depend karta hai — ek die par expected defects ki sankhya. Ise pehle compute karna hume turant batata hai cheezein kitni buri hain: ~3 se upar ka exponent near-total loss ka matlab hai.

Step 2. Formula apply karo: $Y = e^{- 4.5} \approx 0.0111$ . Yeh step kyun? $e^{- 4.5}$ hai "chance ki zero defects yahan land karen" — ek die survive karne ka ek hi tarika.

Answer: lagbhag 1.1% dies good hain.

Verify: Sign aur size ka sanity check — exponent negative hai (yield 1 se neeche honi chahiye ✓) aur magnitude mein bada hai (isliye yield 0 ke paas ✓). Units: $D_{0} A = [mm^{- 2}] [mm^{2}]$ dimensionless hai ✓, toh exponent pure number hai jaise required.

Cell B — splitting yield ko bachata hai

Worked example Ex 2 — Same silicon, 5 mein kaat do

Same $A = 750$ mm² aur $D_{0} = 0.006$ lo, lekin use $N = 5$ chiplets mein split karo, har ek $150$ mm². Per chiplet yield kya hai, aur chiplet ke survive karne ki probability monolith se kitni zyada hai?

Forecast: exponent 5× shrink hoga. Aage padhne se pehle per-chiplet yield guess karo.

Step 1. Naya per-chiplet area $A / N = 750/5 = 150$ mm². Yeh step kyun? Die ko equal pieces mein kaatna area divide karta hai, aur yield sirf area ki parwah karta hai. Har piece ab expected defects ka ek-paanchwa hissa pakadti hai.

Step 2. Exponent $D_{0} \cdot (A / N) = 0.006 \times 150 = 0.9$ . Yeh step kyun? Yeh hai expected defect count per chiplet — 4.5 se ghat kar 0.9 ho gaya.

Step 3. $Y_{chiplet} = e^{- 0.9} \approx 0.4066$ . Yeh step kyun? Same "zero defects" logic, bas chhote area par.

Step 4. Monolith se ratio: $\frac{e ^{- 0.9}}{e ^{- 4.5}} = e^{4.5 - 0.9} = e^{3.6} \approx 36.6$ . Yeh step kyun? Exponentials ko divide karna exponents subtract karta hai — "kitne times better" express karne ka clean tarika, tiny decimals ke bina. Ek chiplet ~37× zyada likely hai good die hone ke liye.

Verify: $e^{- 0.9} \approx 0.407$ hai 0 aur 1 ke beech ✓. Ratio cross-check karo: $0.4066/0.0111 \approx 36.6$ ✓ — $e^{3.6}$ se match karta hai.

Cells C & D — the degenerate inputs (inhe kabhi skip mat karo)

Worked example Ex 3 — Zero area, zero defects, single split

$Y = e^{- D_{0} A}$ aur split formula $e^{- D_{0} A / N}$ ke teen edge cases check karo: (a) $A \to 0$ ; (b) $D_{0} = 0$ (ek perfect process); (c) $N = 1$ (koi split nahi).

Forecast: teenon ko "obvious" physical answer dena chahiye. Kaun si value?

Step 1 (Cell C, $A \to 0$ ). $Y = e^{- D_{0} \cdot 0} = e^{0} = 1$ . Yeh step kyun? Zero area ke die mein koi jagah nahi defect land karne ki, toh woh hamesha good hoga. Formula ko — aur karta hai — yield $= 1$ dena chahiye. Koi bhi formula jo yeh limit fail kare woh galat hoga.

Step 2 (Cell C, $D_{0} = 0$ ). $Y = e^{- 0 \cdot A} = e^{0} = 1$ . Yeh step kyun? Ek flawless process (koi defect nahi) har die yield karta hai. Same limit, doosre variable se reach kiya — acha consistency check.

Step 3 (Cell D, $N = 1$ ). $Y_{chiplet} = e^{- D_{0} A /1} = e^{- D_{0} A}$ . Yeh step kyun? "Ek piece mein split karna" monolith hi hai. Ek correct chiplet formula ko $N = 1$ par monolith formula par wapas collapse hona chahiye — aur karta hai. Isi tarah tum ek generalisation par trust karte ho: isme special case contained hai.

Verify: Teenon $e^{0} = 1$ ya original $e^{- D_{0} A}$ par exactly collapse karte hain — koi approximation nahi, yeh identities hain. ✓

Cell E — $N \to \infty$ limit (hum forever kyun split nahi karte)

Worked example Ex 4 — Agar hum infinitely many chiplets mein kaatein?

Jaise $N \to \infty$ , per-chiplet yield ka kya hota hai? Aur "infinite chiplets" free-lunch answer kyun nahi hai?

Forecast: per-chiplet yield kisi limit ki taraf jaati hai. Kaun si — aur kya yahi poori kahani hai?

Step 1. Per-chiplet exponent $D_{0} A / N \to 0$ jaise $N \to \infty$ . Yeh step kyun? Fixed number $D_{0} A$ ko badhte $N$ se divide karna use zero ki taraf shrink karta hai — har chiplet vanishingly small ho jaata hai.

Step 2. $Y_{chiplet} = e^{- D_{0} A / N} \to e^{0} = 1$ . Yeh step kyun? Tiny chiplets almost certainly defect-free hote hain — yield perfect 100% ke paas pahunch jaati hai.

Step 3 (the catch). Lekin total system cost mein $N$ dies aur $N - 1$ interfaces ki assembly shamil hai. Woh $N$ mein without bound badhti hai. Toh "good silicon" ka curve 1 ke paas flatten hota hai jabki "packaging cost" badhti rehti hai — ek economic optimum finite $N$ par hota hai, infinity par nahi. Yeh step kyun? Formula akela omission se jhooth bolta hai; parent note ka [!mistake] callout ("chiplets hamesha cheaper nahi hote") exactly yahi limit concrete banata hai.

Verify: $N = 1 0^{6}$ plug karo apne numbers ke saath: $e^{- 4.5/1 0^{6}} \approx 0.9999955$ — essentially 1 ✓, limit confirm karta hai jabki common sense confirm karta hai cost explode hoti hai.

Cells F & G — energy per bit (figure dekho)

Figure — Chiplets and multi-die integration

Figure dekho: do links ek bit carry kar rahe hain. Orange short link on-package hai (µm scale); blue long link off-package PCB trace par jaata hai (cm scale). Wire capacitance $C$ length $L$ ke saath badhta hai, aur energy per bit $\frac{1}{2} C V^{2}$ hai, toh jab $V$ fixed ho toh length hi poori kahani hai.

Worked example Ex 5 (Cell F) — Wire half karo, energy half karo

Ek die-to-die link ki length $L_{1} = 2$ mm hai aur $E_{1} = 1.2$ pJ/bit cost karti hai. Ek redesign dies ko itna karib laata hai ki $L_{2} = 1$ mm ho jaye, same voltage ke saath. Naya energy per bit kya hai?

Forecast: length half hoti hai. Kya energy half, quarter, ya same rehti hai?

Step 1. Kyunki $C \propto L$ aur $V$ unchanged hai, $E_{bit} \propto L$ . Toh $\frac{E _{2}}{E _{1}} = \frac{L _{2}}{L _{1}} = \frac{1}{2}$ . Yeh step kyun? $E = \frac{1}{2} C V^{2}$ mein, $V$ fixed rakhne se $E$ poori tarah $C$ par depend karta hai, aur $C$ poori tarah $L$ par depend karta hai. Sirf lengths ka ratio matter karta hai — unknown proportionality constant cancel ho jaata hai.

Step 2. $E_{2} = \frac{1}{2} \times 1.2 = 0.6$ pJ/bit. Yeh step kyun? Half length, half capacitance, half charging energy.

Verify: Units pJ/bit rehte hain ✓. Change ek decrease hai (shorter wire kam cost karni chahiye) ✓ — sign sahi hai.

Cell H — real-world cost word problem

Worked example Ex 7 — Good dies per wafer aur cost each

Ek 300 mm wafer ka usable area $\approx 70, 000$ mm² hai. Process cost hai $8000 per wafer, $D_{0} = 0.005$ defects/mm². (a) Monolithic die $A = 800$ mm² ke liye, wafer per kitne good dies, aur cost per good die? (b) $A = 200$ mm² ke chiplets ke liye repeat karo.

Forecast: kaun sa route cheaper good silicon deta hai? Arithmetic se pehle guess karo.

Step 1 (gross dies). Monolith: $70000/800 = 87.5 \to 87$ whole dies. Chiplet: $70000/200 = 350$ dies. Yeh step kyun? Wafer se sirf whole dies cut ho sakte hain; die area se divide kiya wafer area (round down) batata hai kitne fit hote hain.

Step 2 (yield each). Monolith $Y = e^{- 0.005 \times 800} = e^{- 4} \approx 0.0183$ . Chiplet $Y = e^{- 0.005 \times 200} = e^{- 1} \approx 0.3679$ . Yeh step kyun? $Y = e^{- D_{0} A}$ per die apply karo — gross dies ka woh fraction jo actually kaam karta hai.

Step 3 (good dies). Monolith: $87 \times 0.0183 \approx 1.59 \to\approx 1.6$ good dies. Chiplet: $350 \times 0.3679 \approx 128.8$ good dies. Yeh step kyun? Good dies = gross dies × yield.

Step 4 (cost per good die). Monolith: $8000/1.59 \approx \$ 5031 $. C hi pl e t :$ 8000/128.8 \approx $62.1 $. *Yeh step kyun?* Wafer dono taraf same \$ 8000 cost karta hai; usable dies ki sankhya se divide karna batata hai har good die actually kitna cost karta hai. Monolith almost sab kuch waste karta hai, toh har survivor astronomically expensive hota hai.

Answer: ~$5031 per good monolithic die vs ~$62 per good chiplet — raw silicon cost mein ~81× ka gap (packaging se pehle).

Verify: Chiplet cost monolith se bahut neeche ✓ (parent ki poori thesis se match karta hai). Ratio $5031/62.1 \approx 81$ ✓. Note: yeh packaging ignore karta hai — Ex 9 use wapas daalta hai.

Cell I — exam twist: exponential invert karo

Worked example Ex 8 — Defect density solve karo

Ek fab $A = 120$ mm² die par 60% yield measure karta hai. Defect density $D_{0}$ kya hai?

Forecast: tumhe ek exponential undo karna hoga. Kaun si operation $e^{x}$ undo karti hai?

Step 1. $Y = e^{- D_{0} A}$ se shuru karo $Y = 0.60$ , $A = 120$ ke saath. Yeh step kyun? Hum $Y$ aur $A$ jaante hain; unknown exponent ke andar hai. Use nikalne ke liye hume $e^{(\cdot)}$ ka inverse use karna hoga.

Step 2. Dono sides ka natural log lo: $ln Y = - D_{0} A$ . Yeh step kyun? $ln$ precisely woh function hai jo $e^{(\cdot)}$ undo karta hai: $ln (e^{x}) = x$ . Isi liye hum $ln$ use karte hain $lo g_{10}$ nahi — yeh base- $e$ exponential exactly cancel karta hai, bina kisi stray factor ke.

Step 3. Solve karo: $D_{0} = - \frac{ln Y}{A} = - \frac{ln 0.60}{120} = - \frac{- 0.5108}{120} \approx 0.004257$ defects/mm². Yeh step kyun? $ln 0.60$ negative hai (yield 1 se neeche), aur leading minus use positive flip karta hai — defect density negative nahi ho sakti, toh yeh sign flip ek built-in sanity gate hai.

Answer: $D_{0} \approx 0.00426$ defects/mm².

Verify: Plug back karo: $e^{- 0.004257 \times 120} = e^{- 0.5108} \approx 0.600$ ✓. Positive $D_{0}$ ✓; units defects/mm² ✓.

Cell J — the break-even (chiplets actually kab jeetते hain?)

Worked example Ex 9 — Packaging cost shamil karke crossover dhundho

Silicon cost per good die $62 hai (chiplet, Ex 7 se) lekin har chiplet system ko 4 chiplets chahiye plus packaging jo $P per assembled system cost karti hai. Monolithic good die $5031 hai bina extra packaging ke. Kaun se packaging cost $P par chiplet route jeet jaata hai?

Forecast: chiplet system 4 chiplets use karta hai — guess karo ki $P ke paas hundreds ya thousands of dollars ka headroom hai.

Step 1. Chiplet system silicon cost $= 4 \times \$ 62.1 = $248.4$. Yeh step kyun? Ek working system ko 4 good chiplets chahiye, toh hum chaar survivors ke liye pay karte hain, ek ke liye nahi.

Step 2. Total chiplet cost $= 248.4 + P$ . Win condition: $248.4 + P < 5031$ . Yeh step kyun? "Jeetna" matlab hai chiplet system ki total cost (silicon + packaging) monolith ko undercut kare. Hum packaging wapas add karte hain — exactly woh cost jo parent ke [!mistake] ne warn kiya tha ki bhoolna nahi chahiye.

Step 3. Solve karo: $P < 5031 - 248.4 = \$ 4782.6 $. *Yeh step kyun?* Silicon term subtract karo packaging budget isolate karne ke liye. Jab tak advanced packaging ~\$ 4783 per system se kam cost kare, chiplets yahan cheaper hain.

Answer: chiplets jeetте hain jab packaging $P < $4783 per system ho. (Real packaging far below this hai, toh chiplets clearly jeetते hain bade die ke liye — lekin die shrink karo aur monolith cost drop hoti hai, yeh headroom khaata hai, isi liye chhote dies monolithic rehte hain.)

Verify: $P = 4782.6$ par: chiplet total $= 248.4 + 4782.6 = 5031.0 =$ monolith cost — exact break-even ✓. Kisi bhi chhote $P$ ke liye, chiplet total strictly less hai ✓.

Recall Matrix par quick self-test

Har ek kaun se cell mein belong karta hai? " $Y = e^{- D_{0} A}$ with $A = 750$ , yield ~1%" ::: Cell A (big monolith) " $N = 1$ split formula ko monolith reduce karta hai" ::: Cell D (degenerate split) "Off-package bit on-package bit se 10× cost karta hai" ::: Cell G (energy order of magnitude) " $D_{0}$ solve karne ke liye $ln$ lo" ::: Cell I (invert the exponential) "Woh packaging budget dhundho jahan chiplets break even karte hain" ::: Cell J (break-even)

Connections

Chiplets and multi-die integration — woh parent topic jise yeh examples drill karte hain.
Wafer yield and defect density — Cells A–E, H, I mein use hone wala $e^{- D_{0} A}$ model.
Interconnect energy and dark silicon — Cells F, G mein $\frac{1}{2} C V^{2}$ energy math.
Advanced packaging (2.5D 3D interposers) — woh packaging cost jo Cell J mein wapas add ki gayi.
Moore's Law and its slowdown — isi liye reticle limit splitting force karti hai.
Memory bandwidth and HBM — jahan short 3D links bandwidth mein pay off karte hain.
Heterogeneous integration — nodes mix karna, chiplets jeetने ka ek aur reason.