Visual walkthrough — Chiplets and multi-die integration
6.5.1 · D2· Hardware › Advanced & Emerging Architectures › Chiplets and multi-die integration
Prerequisites jinpar hum rely karte hain: Wafer yield and defect density aur parent topic. Yeh Wafer yield and defect density ka picture-first companion hai.
Step 1 — Wafer aur raisins
KYA: Hum defects ko wafer par randomly scattered dots ki tarah picture karte hain.
KYUN: Kisi bhi math se pehle, humein ek mental model chahiye. Agar ek bhi defect kisi chip ke andar land karta hai, toh woh chip (simple model mein) dead hai. Toh poori story ek sawaal tak reduce ho jaati hai: kitni likely hai ki ek chip par zero dots hon?
PICTURE: Neeche, peach disc wafer hai; magenta dots defects hain jo randomly sprinkle hue hain.

Step 2 — Ek chip par defects count karna: expected number
KYA: Hum sabse important quantity form karte hain, ek die par expected defect count:
Term by term: hai kitna thick sprinkle hai, hai kitna area tumne sprinkle ke saamne expose kiya, aur unka product (Greek letter "lambda") hai average par kitne defects land hone chahiye.
kyun, actual count kyun nahi? Kyunki actual count random hota hai — kabhi , kabhi . Hum ek single wafer predict nahi kar sakte, lekin hum average zaroor predict kar sakte hain. woh anchor hai jispar baaki sab kuch tikta hai.
PICTURE: Ek hi sprinkle par alag-alag area ke do chips. Bada wala zyada dots pakadne ki expect karta hai. Yahi hai "big dies are doomed" ka poora intuition.

Step 3 — Poisson formula kyun? (tool, justified)
KYA: Hum probability likhte hain exactly defects milne ki ek aise die par jiska expected count hai:
Left to right padhte hain:
- — expected count ko power pe raise kiya: bada bade ko zyada likely banata hai.
- — ek shrinking factor (; negative exponent matlab "one se kam"). Yeh total probability ko exactly par rakhta hai.
- — " factorial" . Yeh un kaafi saare orderings ke liye correct karta hai jinmein same defects aa sakte the.
Yeh shape kyun? Ise memorize mat karo — bas trust karo ki teen assumptions yahi exact form force karti hain. Humein agle step mein sirf ki ek value chahiye.
PICTURE: aur ke liye Poisson bar chart. Notice karo: jaise badhta hai, par bar (hamara "good chip" bar, highlighted) tezi se chota hota jaata hai.

Step 4 — Ek achha chip matlab ZERO defects: plug in karo
KYA: Poisson formula mein substitute karo:
Yeh do simplifications kyun:
- — kuch bhi zero power par hota hai.
- — zero ka factorial define kiya gaya hai.
Top-left aur bottom dono par collapse ho jaate hain, sirf decay factor bachta hai:
PICTURE: Poora curve area ke against, Step 3 ka bar uspar trace kiya gaya — dikhate hue ki poora yield curve literally "zero defects" bar ki height hai jaise slide karta hai.

Step 5 — Exponential feel karo: monolithic die
KYA: Parent ke numbers lo: defects/mm² aur ek monolithic die mm² ka.
Term by term: expected defects per die. Chaar expected defects ka matlab hai zero ki chance hai. Har sau mein ninyanve giant dies dead paida hoti hain.
Pehle yeh kyun dikhayein? Taaki Step 6 mein rescue ke paas koi brutal cheez ho jisse rescue karna ho.
PICTURE: Sprinkle par ek bada die outline — almost har copy mein kam se kam ek dot hai. Woh rare survivor circle mein hai.

Step 6 — Rescue: chiplets mein split karo
KYA: area ke ek chiplet ki yield:
Step 4 se sirf ek hi change hai: exponent mein ki jagah aa gaya — ek chhota expected count, toh ek badi survival probability.
ke saath, mm²:
Ab expected defect per chiplet, toh bachte hain — monolith se kareeban 20× behtar.
Yeh fairness se zyada kyun hai: Hum 98%-doomed giant kabhi banate hi nahi. Hum sirf achhe chote dies rakhte hain (known-good die), phir unhe ek package mein glue karte hain.
PICTURE: Wahi sprinkle, ab die ko 4 tiles mein kaata gaya. Kharaab tiles (dot ke saath) shaded out, achhe tiles glowing. Zyaatar tiles survive karte hain.

Step 7 — Edge case: jab splitting HELP nahi karta
KYA: Ek chota die compare karo, maano mm², :
Pehle se achhe hain. Do mein split karo (): . Ek modest gain — aur ab tum interposer + assembly + double I/O area ke liye paisa doge. Chiplets yahan zyada mehnge pad sakte hain.
Yeh kyun include kiya? Contract: har case cover karo. Chiplets free magic nahi hain. Wafer yield and defect density curve ke paas flat hai, toh payoff sirf wahan milta hai jahan curve steep ho — bada .
PICTURE: – curve do regions ke annotations ke saath: origin ke paas ek flat "splitting barely helps" zone (violet) aur bade area par ek steep "splitting rescues you" zone (magenta).

Step 8 — Degenerate cases: perfect aur worst wafers
KYA: Model ko uske edges tak push karo:
| Input | Plug in | Result | Matlab |
|---|---|---|---|
| (flawless wafer) | Har die achha — splitting pointless. | ||
| (vanishing die) | Infinitely small dies kabhi defect nahi pakdte. | ||
| (giant die) | Kuch nahi bachta — reticle limit aur yield dono chilla rahe hain "ruko." |
KYUN: Yeh trivia nahi hain — yeh sanity checks hain jo prove karte hain ki real silicon jaisa behave karta hai. Ek formula jo ya deta woh bakwaas hota; hamara always mein rehta hai.
PICTURE: Single curve apne do flat asymptotes ke saath: left par se chipka hua, right par se chipka hua, kabhi band nahi chhod raha.

Ek-picture summary

Recall Poori walkthrough ki Feynman retelling
Cookie dough par raisins sprinkle karo — tum aim nahi kar sakte. Ek raisin us cookie ko kharab kar deta hai jisme woh land kare. Agar tum ek enormous cookie () bako, toh almost certain hai ki woh ek raisin pakadega, toh almost har giant cookie trash hai — humne sum kiya: sirf bachte hain (). Yeh math jo keh raha hai woh sirf hai "kitni likely hai zero raisins?", aur random sprinkles ke liye woh answer hai — ek exponential, matlab bade cookies ko aur tezi se aur tezi se punish milti hai. Ab chaar chote cookies () bako usi dough se: har ek raisins sirf ek-chauthai kitni baar pakadta hai, toh bachte hain (), aur hum har ek ko taste-test karte hain aur kharaab wale hata dete hain achhe wale glue karne se pehle. Lekin agar cookie already tiny thi (), toh woh waise bhi theek thi, toh splitting mushkil se help karta hai aur tum glue ka extra paisa bas dete ho. Aur extremes behave karte hain: koi raisins nahi → sab bachte hain; zero size ki cookie → always fine; infinite cookie → always doomed. Woh last curve — se start karke, par slide hoti, kabhi zero se neeche ya one se upar nahi jaati — hai hi chiplets banane ki poori story.
Connections
- Wafer yield and defect density — curve ka ghar, jise humne yahan rebuild kiya.
- Advanced packaging (2.5D 3D interposers) — woh cost jo tum chiplets mein split karne par dete ho.
- Moore's Law and its slowdown — bade monolithic dies ne scale karna kyun band kar diya.
- Heterogeneous integration — process nodes mix karna, split karne ki ek aur wajah.