Thermal design power (TDP): Worked examples — Hinglish deep dive

6.4.3 · D3 · Hardware › Power, Thermal & Reliability › Thermal design power (TDP)

Ye page Thermal design power (TDP) ke liye ek drill sheet hai. Hum yahan theory se scratch se nahi padhayenge — balki hum har tarah ki situation dhundhte hain jo thermal-design equation throw kar sakti hai, aur har ek ke liye ek clean example solve karte hain. End tak koi bhi number configuration tumhe surprise nahi karni chahiye.

Shuru karne se pehle, ek equation ko re-anchor karte hain jis par sab kuch tika hai, simple words mein.

Definition Ek law, plus uska sign convention

Heat "downhill" flow karti hai ek hot chip se cool air ki taraf, exactly jaisa pani downhill flow karta hai ya current ek resistor ke across flow karta hai. Jo steepness chahiye woh hai temperature difference $Δ T$ (°C mein), "flow" hai power $P$ (watts mein, W — ek watt yaani har second ek joule heat nikalna), aur "flow ki difficulty" hai thermal resistance $R_{θ}$ (°C per watt mein — har extra watt jitna shed karna ho, chip utne degree zyada hot ho jaati hai).

$Δ T = P \times R_{θ}$

Teen tarike se rearrange, kyunki har problem mein se do milte hain aur teesra chhupaata hai: $P = \frac{Δ T}{R _{θ}}, R_{θ} = \frac{Δ T}{P}, Δ T = P R_{θ}$

Sign convention (yaad karo): hum hamesha likhte hain $Δ T = T_{hot} - T_{cold} = T_{j} - T_{ambient}$ , taaki chip se bahar jaati heat se $Δ T$ positive bane. Physical thermal resistance $R_{θ}$ hamesha positive hota hai (ek real material heat ko sirf resist kar sakta hai, pump nahi). Isliye, $P > 0$ ke saath:

$Δ T > 0$ → normal case, heat chip → air flow karta hai.
$Δ T = 0$ → chip exactly air temperature par hai, koi net flow nahi.
$Δ T < 0$ → "budget" negative hai kyunki air chip ke limit se zyada hot hai; yeh nahi hai reverse heat flow tumhare cooler ke andar aur nahi hai calculation error — yeh ek flag hai ki koi bhi passive cooler chip ko spec mein nahi rakh sakta (tumhe active refrigeration chahiye hoga). Hum isse Case F mein dekhte hain.

Figure s01 — thermal ladder. Chaar horizontal black lines rungs ki tarah stack hain: sabse upar wala rung chip junction hai $T_{j} = 100 ° C$ par (sabse garam), phir case, phir heatsink (sink), aur sabse neecha rung ambient air hai $T_{ambient} = 30 ° C$ par (sabse thanda). Left par ek lamba red arrow "heat flow" label ke saath sabse chaar rungs ke through neeche point karta hai — heat hamesha top-to-bottom, hot to cold travel karti hai. Har do rungs ke beech ek chhota arrow hai jis par resistance annotated hai aur woh temperature drop jo Examples 1–5 ke $95 W$ chip ke liye hai: $R_{θ, JC} = 0.25$ se $23.75 ° C$ drop hota hai, $R_{θ, CS} = 0.10$ se $9.5 ° C$ drop hota hai, aur red bottom rung $R_{θ, SA} = 0.387$ se $36.75 ° C$ drop hota hai. Ye teen drops stack up hoke total $70 ° C$ rise banate hain. Har rung ek resistance hai jis se heat neeche "climb" karti hai, aur resistances series mein add hote hain — same heat sabse ek ke baad ek sab se pass hoti hai:

$R_{θ, total} = R_{θ, JC} + R_{θ, CS} + R_{θ, SA}$

$R_{θ, JC}$ — Junction-to-Case, chip package mein baked in.
$R_{θ, CS}$ — Case-to-Sink, thermal-paste layer.
$R_{θ, SA}$ — Sink-to-Ambient, heatsink + fan (woh part jo tum choose karte ho — red mein draw kyunki Examples 1, 2 aur 4 mein yahi knob hai tumhare control mein).

Woh "inhe add karo" rule hi poora reason hai kyun series resistances yahan matter karti hain — dekho Heatsink design and thermal resistance. Is ladder ko apne paas khula rakho: neeche har example sirf yahi picture hai alag numbers ke saath rungs par.

The scenario matrix

Yeh har distinct tarah ka case hai jo yeh topic produce kar sakta hai. Neeche har worked example us cell ke saath tagged hai jisme woh fit hota hai.

#	Case class	Kya ise alag banata hai	Example
A	Unknown resistance solve karo	$Δ T$ , $P$ , kuch $R$ s diye hain → missing $R$ nikalo	Ex 1
B	Temperature solve karo	$R$ s aur $P$ diye hain → junction temp nikalo, kya throttle hoga?	Ex 2
C	Ratio / scaling (koi absolute values nahi)	Overclock se $V^{2} f$ scaling	Ex 3
D	Degenerate: perfect cooler ( $R \to 0$ )	limiting behaviour, zero resistance	Ex 4
E	Degenerate: no cooler / zero power	$P = 0$ ya $R \to \infty$ edge cases	Ex 5
F	Hot-ambient / budget ka sign	$T_{ambient}$ $T_{j, max}$ ke paas ya usse upar → budget zero ya negative	Ex 6
G	Real-world word problem	TDP vs measured wall power	Ex 7
H	Exam-style twist	Fixed cooler mein fit hone ke liye undervolt (reverse ratio)	Ex 8

Case A — Missing resistance solve karo

Worked example Example 1 — Heatsink budget (cell A)

Ek CPU ka $TDP = 95 W$ hai aur $T_{j, max} = 100 ° C$ . Room air $T_{ambient} = 30 ° C$ hai. Package deta hai $R_{θ, JC} = 0.25 ° C / W$ aur paste deta hai $R_{θ, CS} = 0.10 ° C / W$ . Sabse bada heatsink $R_{θ, SA}$ kya hai jo tum use kar sakte ho aur phir bhi throttle na ho?

Forecast: guess karo — kya answer $0.5 ° C / W$ se upar ya neeche hoga? Likh lo.

Temperature budget $Δ T = 100 ° C - 30 ° C = 70 ° C$ . Yeh step kyun? Yeh total "downhill drop" available hai — figure mein ladder ki poori height. Hum junction ko $T_{j, max}$ se aage kabhi nahi jaane de sakte, toh $Δ T$ hamaara poora allowance hai.
Total resistance allowed $R_{θ, total} = \frac{Δ T}{TDP} = \frac{70 ° C}{95 W} = 0.7368 ° C / W$ . Yeh step kyun? $Δ T = P R_{θ}$ se, drop exceed kiye bina poore stack mein sabse zyada resistance $Δ T / P$ ho sakti hai. Units: $° C \div W = ° C / W$ . (Yahan $TDP$ chip ki power $P$ hai — same number.)
Fixed rungs subtract karo $R_{θ, SA} = 0.7368 ° C / W - 0.25 ° C / W - 0.10 ° C / W = 0.3868 ° C / W$ . Yeh step kyun? Series resistances add hoti hain (ladder ke top do rungs fixed hain), toh red heatsink rung ko jo bhi bacha hai woh milta hai. Teeno quantities °C/W carry karti hain, toh subtraction dimensionally clean hai.

Answer: $R_{θ, SA} \leq 0.387 ° C / W$ .

Verify: temperature rebuild karo. $95 W \times (0.25 + 0.10 + 0.3868) ° C / W = 95 \times 0.7368 = 70 ° C$ rise → $30 + 70 = 100 ° C = T_{j, max}$ . ✓ Units: $W \times \frac{° C}{W} = ° C$ . ✓

Case B — Temperature solve karo (kya throttle hoga?)

Worked example Example 2 — Kya throttle hoga? (cell B)

Same chip (TDP $95 W$ , $T_{j, max} = 100 ° C$ , ambient $30 ° C$ , $R_{θ, JC} = 0.25 ° C / W$ , $R_{θ, CS} = 0.10 ° C / W$ ) ek real cooler ke saath fit kiya gaya hai jo $R_{θ, SA} = 0.45 ° C / W$ rated hai. Kya yeh throttle karega?

Forecast: $0.45$ us $0.387$ se bada hai jo allowed tha. Compute karne se pehle answer feel karo.

Total resistance $R_{θ, total} = 0.25 ° C / W + 0.10 ° C / W + 0.45 ° C / W = 0.80 ° C / W$ . Yeh step kyun? Ab ladder ka har rung hume pata hai, toh poore path ke liye unhe add karo (sab °C/W mein).
Predicted rise $Δ T = P R_{θ} = 95 W \times 0.80 ° C / W = 76 ° C$ . Yeh step kyun? Law ki forward direction — heat times resistance temperature climb deta hai (ladder ab Ex 1 se lamba hai). Units: $W \times ° C / W = ° C$ .
Junction temperature $T_{j} = T_{ambient} + Δ T = 30 ° C + 76 ° C = 106 ° C$ . Yeh step kyun? Chip us air se $Δ T$ upar hai jisme heat dump hoti hai — bottom rung se shuru karo aur climb karo.
Compare karo $106 ° C > 100 ° C = T_{j, max}$ .

Answer: Haan — yeh $T_{j, max}$ se $6 ° C$ zyada hai, toh Thermal throttling kick in hoti hai aur chip frequency drop karta hai jab tak uski power budget ke andar nahi aa jaati.

Verify: break-even resistance $0.7368 ° C / W$ tha; humne $0.80 > 0.7368$ use kiya, toh over-temperature guaranteed hai — consistent. ✓

Case C — Ratio / scaling (overclock)

Definition Power law mein do mystery symbols, pictures mein

Dynamic-power law hai $P_{dyn} = α C V^{2} f$ . Inhe use karne se pehle do symbols ko earn karna padega:

$α$ (activity factor) — $0$ aur $1$ ke beech ek fraction jo batata hai kitne share transistors actually flip karte hain har clock tick par. Ek wall of light-switches socho: agar aadhe ek given tick par toggle karte hain, $α = 0.5$ . Kuch switch nahi → $α = 0$ → koi dynamic power nahi.
$C$ (capacitance) — kitna electrical "charge bucket" har switching node ko fill aur empty karna padta hai. Bada bucket → har flip mein zyada charge → zyada heat. Yeh chip ke physical layout se fix hota hai, toh jab tum overclock karte ho tab yeh nahi badlata.

Neeche figure dikhata hai kyun hume sirf ratio chahiye: $α$ aur $C$ overclock se pehle aur baad same hain, toh cancel ho jaate hain aur gayab ho jaate hain — sirf $V^{2} f$ bachta hai poore power change ko explain karne ke liye.

Figure s02 — kyun sirf $V^{2} f$ matter karta hai. Horizontal axis clock frequency $f$ GHz mein hai; vertical axis dynamic power $P = (α C) V^{2} f$ arbitrary units mein hai ( $α C$ ko $1$ set karke). Do straight lines origin se rise karti hain: ek black line "before" voltage $V = 1.10 V$ ke liye aur ek steeper red line "after" voltage $V = 1.25 V$ ke liye — red line steeper hai kyunki zyada voltage slope ko $V^{2}$ se multiply karta hai. Ek black dot purana operating point $3.0 GHz$ par black line par mark karta hai; ek red dot naya operating point $4.0 GHz$ par red line par mark karta hai. Text note yaad dilata hai ki $α C$ sirf dono lines ki height ko same factor se rescale karta hai, toh ratio $P_{new} / P_{old}$ mein cancel ho jaata hai — sirf $V^{2} f$ bachta hai poore power change ko explain karne ke liye (dekho Power consumption in CMOS circuits).

Worked example Example 3 — Overclock power scaling (cell C)

Ek chip $TDP = 65 W$ par $3.0 GHz$ aur $1.10 V$ par run karti hai. Tum $4.0 GHz$ aur $1.25 V$ par overclock karte ho. Dynamic power dominate karta hai aur switching activity unchanged hai. Naya heat output estimate karo.

Forecast: power roughly $V^{2} f$ follow karta hai. Voltage ~14% upar, frequency ~33% upar. Multiplier guess karo.

Dynamic-power law recall karo $P_{dyn} = α C V^{2} f$ , $α$ aur $C$ upar picture ki tarah. Yeh step kyun? $α$ aur $C$ ki absolute values unknown hain, lekin woh ratio mein cancel ho jaate hain — toh hum ratio set up karte hain, raw calculation nahi.
Ratio banao $\frac{P _{new}}{P _{old}} = \frac{V _{new}^{2} f _{new}}{V _{old}^{2} f _{old}} = \frac{( 1.25 ) ^{2} \times 4.0}{( 1.10 ) ^{2} \times 3.0}$ . Yeh step kyun? $α C$ top aur bottom par identical hai (same chip, same workload), toh gayab ho jaata hai — yahi reason hai kyun hum ratio use karte hain $C$ guess karne ki jagah. Ratio dimensionless hai (volts² aur GHz top-against-bottom cancel hote hain).
Calculate karo $= \frac{1.5625 \times 4.0}{1.21 \times 3.0} = \frac{6.25}{3.63} = 1.7218$ . Yeh step kyun? Bas arithmetic — voltages ko square karo, frequency se multiply karo.
TDP scale karo $P_{new} \approx 1.7218 \times 65 W = 111.9 W$ .

Answer: ≈ 112 W — original ka lagbhag $1.72 \times$ . Tumhara $65 W$ cooler ab badly undersized hai (Overclocking and voltage scaling).

Verify: $V^{2}$ term akela $(1.25/1.10)^{2} = 1.291$ hai; $f$ term $4.0/3.0 = 1.333$ hai; product $1.291 \times 1.333 = 1.721$ . ✓ Step 3 se match karta hai.

Case D — Degenerate: perfect cooler

Worked example Example 4 — Ideal heatsink,

$R_{θ, SA} \to 0$ (cell D) Example 2 ke cooler ko fantasy limit tak push karo: ek infinitely good heatsink jiska $R_{θ, SA} = 0$ hai. Same $95 W$ chip, ambient $30 ° C$ . Kya junction temperature result hogi, aur kya chip ab unbreakable hai?

Forecast: kya chip room temperature tak aa jaati hai? Padhne se pehle guess karo.

Remaining resistance $R_{θ, total} = 0.25 ° C / W + 0.10 ° C / W + 0 = 0.35 ° C / W$ . Yeh step kyun? Ladder ke red rung ko zero set karna sirf wahi rung delete karta hai — top do rungs $R_{θ, JC}$ aur $R_{θ, CS}$ rehte hain, kyunki heat ko silicon se bahar crawl karna padta hai aur pehle paste se guzarna padta hai.
Junction rise $Δ T = 95 W \times 0.35 ° C / W = 33.25 ° C$ . Yeh step kyun? Path ke irreducible part par forward law phir se.
Junction temperature $T_{j} = 30 ° C + 33.25 ° C = 63.25 ° C$ .

Answer: $T_{j} = 63.25 ° C$ — comfortably safe, lekin nahi room temperature. Floor package aur paste set karta hai jo tum kabhi delete nahi kar sakte.

Verify: jaise $R_{θ, SA} \to 0$ , $R_{θ, total} \to 0.35 ° C / W$ ; koi bhi positive heatsink resistance sirf $Δ T$ mein add karti hai, toh $63.25 ° C$ sabse thanda hai jo junction kabhi $95 W$ par ho sakta hai. ✓ Lower-bound sanity check pass.

Case E — Degenerate: no power, ya no cooler

Worked example Example 5 — Do zero-limits (cell E)

Same chip. Do edge questions: (a) CPU $P = 0 W$ par idle karta hai (imagine fully asleep). $T_{j}$ kya hogi? (b) Tum heatsink bilkul bhool jaate ho, toh sink-to-air path effectively open hai: $R_{θ, SA} \to \infty$ . $T_{j}$ ka kya hoga?

Forecast: inme se ek boring answer deta hai aur ek runaway deta hai. Guess karo kaun sa kaun sa hai.

Part (a): $P = 0$ plug karo $Δ T = P R_{θ} = 0 W \times R_{θ} = 0 ° C$ mein. Yeh step kyun? Koi heat generate nahi ho rahi, toh sustain karne ke liye koi temperature drop nahi hai — poora ladder zero height tak collapse ho jaata hai.
Toh $T_{j} = T_{ambient} + 0 = 30 ° C$ . Yeh step kyun? Kuch bhi shed nahi karna toh chip simply room air ke saath equalise ho jaati hai — degenerate "no source" case.
Part (b): $R_{θ, SA} \to \infty$ jaane do $Δ T = P R_{θ, total}$ mein. Kyunki $R_{θ, total} = 0.35 ° C / W + R_{θ, SA}$ hai, hume $Δ T \to \infty$ milta hai. Yeh step kyun? Ek open thermal path (ladder ka bottom rung infinity tak stretch) matlab heat bina limit ke pile up hoti hai — math unbounded temperature predict karta hai.
Reality clamp: chip $T_{j, max} = 100 ° C$ par almost instantly pahunch jaati hai, hard throttle karti hai, aur agar woh fail ho, uska thermal shutdown trip karta hai.

Answer: (a) $T_{j} = 30 ° C$ (ambient ke barabar). (b) $T_{j} \to \infty$ mathematically → practice mein immediate throttle / shutdown.

Verify: (a) $30 + 95 \times R_{θ}$ with power $0$ set se kisi bhi $R_{θ}$ ke liye $30$ milta hai. ✓ (b) $Δ T = 95 \times (0.35 + R)$ bina bound ke grow karta hai jaise $R$ grow karta hai. ✓

Case F — Hot ambient / budget ka sign

Worked example Example 6 — Jab room bahut hot ho (cell F)

Ek data-center rack ek $150 W$ chip run karta hai jiska $T_{j, max} = 95 ° C$ hai. Inlet air $95 ° C$ hai kyunki aisle cooling fail ho gayi. Kitna temperature budget bacha hai, aur kaun sa heatsink ise bacha sakta hai?

Forecast: room junction limit par hai. Kya koi cooler kaam kar sakta hai?

Budget $Δ T = T_{j, max} - T_{ambient} = 95 ° C - 95 ° C = 0 ° C$ . Yeh step kyun? Allowance ceiling aur air ke difference se aata hai. Yahan dono coincide karte hain, toh zero room hai — ladder mein kaam karne ki koi height nahi.
Required total resistance $R_{θ, total} = \frac{Δ T}{P} = \frac{0 ° C}{150 W} = 0 ° C / W$ . Yeh step kyun? $Δ T = 0$ rakhte hue $150 W$ push karne ke liye, resistance exactly zero honi chahiye — physically impossible, kyunki bare die ka bhi $R_{θ, JC} > 0$ hota hai.
Aur bhi garam air — maan lo inlet $100 ° C$ tak badh jaata hai: $Δ T = 95 ° C - 100 ° C = - 5 ° C$ . Yeh step kyun? Hamare sign convention se, $Δ T < 0$ matlab air allowed junction se zyada hot hai.
Required resistance ab negative ho jaata hai $R_{θ, total} = \frac{Δ T}{P} = \frac{- 5 ° C}{150 W} = - 0.0333 ° C / W$ . Yeh step kyun? Formula negative resistance nikalta hai. Ise sahi se samjho: real material ka $R_{θ}$ hamesha $\geq 0$ hota hai (heat sirf resist hoti hai, pump nahi hoti), toh required $R_{θ} < 0$ kisi bhi passive cooler se achievable nahi hai. Yeh nahi hai reverse heat flow tumhare heatsink ke andar aur nahi hai arithmetic mistake — yeh equation ka tarika hai yeh kehne ka ki "active refrigeration ke bina impossible hai jo gradient ke against heat pump kare."

Answer: $95 ° C$ inlet par required $R_{θ}$ exactly $0$ hai (impossible); $95 ° C$ se upar budget negative hai aur required $R_{θ}$ negative hai ( $100 ° C$ inlet par $- 0.033 ° C / W$ ) — matlab passive cooling bilkul fail ho jaati hai. Fix room ko fix karna hai (ya refrigeration loop add karna), heatsink ko nahi.

Verify: budget sign exactly tab flip hota hai jab $T_{ambient} = T_{j, max}$ : inlet $94 ° C$ ke liye, $Δ T = + 1$ (tiny but positive → tiny positive $R_{θ}$ ); $96 ° C$ ke liye, $Δ T = - 1$ (negative → negative $R_{θ}$ ). ✓ Aur $- 5/150 = - 0.0333 ° C / W$ . ✓

Case G — Real-world word problem

Worked example Example 7 — TDP vs wall meter (cell G)

Ek laptop CPU $15 W$ TDP rated hai. Ek plug-in meter benchmark ke dauran 48 W wall par read karta hai. Tumhara dost chillata hai "TDP ek jhooth hai!" Numbers reconcile karo.

Forecast: kya $48 W$ ek $15 W$ TDP ko contradict karta hai? (Nahi karta — figure out karo kyun.)

TDP sirf chip ki heat hai. $15 W$ CPU ke thermal output ko cooling design ke liye describe karta hai, aur kuch nahi. Yeh step kyun? TDP ka jawab hai "cooler ko kitni heat move karni hai," "poora laptop kitna khata hai" nahi.
Baaki consumers list karo. GPU $\approx 14 W$ , display backlight $\approx 8 W$ , RAM + SSD + board $\approx 5 W$ . Yeh step kyun? Har subsystem CPU ke thermal spec se independently power draw karta hai.
Supply loss add karo. Ab tak sum $= 15 + 14 + 8 + 5 = 42 W$ ; charger/PSU ~ $88%$ efficient hai, toh wall draw $= 42 W /0.88 = 47.7 W$ . Yeh step kyun? Wall meter power conversion losses se pehle dekhta hai, toh internal total ko plug tak inflate karne ke liye efficiency se divide karte hain. (Efficiency dimensionless hai, toh watts, watts rehte hain.)

Answer: Wall par $\approx 48 W$ ek $15 W$ CPU TDP ke saath fully consistent hai — koi contradiction nahi, alag quantities hain.

Verify: $42/0.88 = 47.73 W \approx 48 W$ measured. ✓ Aur CPU ka share $15 W$ sirf $\approx 31%$ wall reading ka hai, exactly kyun TDP $\neq =$ system power. ✓

Case H — Exam-style twist (scaling reverse karo)

Worked example Example 8 — Fixed cooler mein fit hone ke liye undervolt (cell H)

Tumhara cooler aur case sirf 95 W shed kar sakte hain. Stock mein, chip $125 W$ hai $1.30 V$ , $4.5 GHz$ par. Tum frequency rakhte ho (tumhe speed chahiye) lekin undervolt karte ho. Assuming dynamic power dominate karta hai aur $P \propto V^{2} f$ , kaun sa voltage power ko 95 W tak laata hai?

Forecast: humein power $95/125 = 0.76$ cut karni hai. Fixed frequency ke saath, sirf $V^{2}$ ise drop kar sakta hai. Computing se pehle naya voltage guess karo.

Frequency fix karo, voltage isolate karo. Kyunki $f$ unchanged hai, ratio $\frac{P _{new}}{P _{old}} = \frac{V _{new}^{2} f}{V _{old}^{2} f} = \frac{V _{new}^{2}}{V _{old}^{2}}$ . Yeh step kyun? $f$ terms cancel ho jaate hain (aur $α$ aur $C$ bhi pehle ki tarah), toh poori power reduction voltage-squared term se aani chahiye — wahi ek free knob bacha hai.
Voltage ratio solve karo $\frac{V _{new}^{2}}{V _{old}^{2}} = \frac{95 W}{125 W} = 0.76 \Rightarrow \frac{V _{new}}{V _{old}} = 0.76 = 0.8718$ . Yeh step kyun? Square root se square undo karo — yahi reason hai kyun square root aata hai: power voltage mein quadratic hai, toh power fix karna matlab ratio ko root karna. $0.76$ dimensionless hai (watts cancel), toh uska root bhi hai.
New voltage $V_{new} = 0.8718 \times 1.30 V = 1.133 V$ . Yeh step kyun? Old voltage ko abhi mila ratio se multiply karo absolute value land karne ke liye.

Answer: $\approx 1.13 V$ par undervolt karo aur tum $4.5 GHz$ rakhte ho jabki $95 W$ cooler ke andar fit ho jaate ho — efficiency tune ka essence (Overclocking and voltage scaling, Turbo Boost and power states).

Verify: forward-check $(1.133/1.30)^{2} \times 125 = (0.8715)^{2} \times 125 = 0.7595 \times 125 = 94.9 W \approx 95 W$ . ✓ Ratio ke units dimensionless hain, aur $V$ times ek pure number volts rehta hai. ✓

Recall Quick self-test

Ek 100 W chip, $T_{j, max} = 90 ° C$ , ambient $40 ° C$ : sabse bada total $R_{θ}$ ? ::: $Δ T = 50 ° C$ , toh $R_{θ} = 50/100 = 0.5 ° C / W$ . Perfect heatsink junction ko ambient tak kyun DROP NAHI karta? ::: Internal $R_{θ, JC}$ aur paste $R_{θ, CS}$ abhi bhi rise force karte hain; sirf $R_{θ, SA}$ zero gaya. Temperature budget kab negative hota hai, aur iska kya matlab hai? ::: Jab $T_{ambient} > T_{j, max}$ ; ek negative required $R_{θ}$ matlab koi passive cooler kaam nahi karta — reverse heat flow nahi, math error nahi. Overclock $f$ fixed rakhta hai aur tum power $\times 0.64$ chahte ho; naya voltage ratio? ::: $0.64 = 0.8$ , toh old voltage ka $0.8 \times$ . Kya TDP instantaneous power ke barabar hai? ::: Nahi — TDP sustained power hai jiske liye cooler size kiya jaata hai; instantaneous turbo power briefly isse exceed kar sakti hai.