Exercises — Dynamic voltage and frequency scaling (DVFS)

Dynamic power: $P_{\text{dyn}}=C_{\text{eff}}{V}^{2}f$ — energy per switch ($\frac{1}{2}C{V}^2$) times switches per second ($\alpha f$). Static (leakage) power: $P_{\text{leak}}=V\cdot I_{\text{leak}}$ — current that trickles through powered-on transistors even when nothing switches. Task energy at fixed work $N$ cycles: $E=P\cdot t$ where $t=N/f$. For pure dynamic power this collapses to $E_{\text{dyn}}=C_{\text{eff}}{V}^{2}N$ — the frequency cancels, so energy depends on voltage, not speed (as long as leakage is ignored).

WHAT: Read off the exponents. $f$ appears to the power 1, $V$ to the power 2. Double $f$: $P\to C_{\text{eff}}{V}^2(2f)=2P$. Power doubles (×2). Double $V$: $P\to C_{\text{eff}}(2V{)}^{2}f=4C_{\text{eff}}{V}^{2}f=4P$. Power quadruples (×4). WHY it matters: the quadratic $V^2$ is the whole reason DVFS lowers voltage, not just frequency.

Lowest power: P3 (0.90 V, 2.0 GHz, 22 W). Highest frequency: P0 (1.35 V, 4.0 GHz, 95 W). P0 is "sprint," P3 is "coast." See Clock generation and PLs for how the frequency is actually generated, and Voltage regulators for how the voltage is delivered.

Because lower voltage makes transistors switch slower ($t_{\text{delay}}\propto V_{dd}/(V_{dd}-V_{th}{)}^2$), so below some voltage the logic cannot finish before the next clock edge — the chip produces wrong results. Voltage and frequency must scale together.

Power: $P_2=C_{\text{eff}}(k{V}_1{)}^2(k{f}_1)=k^3{P}_1=0.75^3{P}_1=0.4219P_1$. Power drops by $1-0.4219=57.8\%$. Energy: the task takes $t_2=N/f_2=N/(k{f}_1)$, longer by $1/k$. So $E_2=P_2{t}_2=k^3{P}_1\cdot \frac{t_1}{k}=k^2{E}_1=0.5625E_1$. Energy drops by $1-0.5625=43.75\%$. WHY the difference: power scales as $k^3$ (three factors of $k$), but energy loses one factor of $k$ back because the slower clock stretches the runtime. Net: energy $\propto k^2$.

$\frac{P_{\text{P3}}}{P_{\text{P1}}}=\frac{V_3^2{f}_3}{V_1^2{f}_1}=\frac{0.90^2\cdot 2.0}{1.20^2\cdot 3.5}=\frac{0.81\cdot 2.0}{1.44\cdot 3.5}=\frac{1.62}{5.04}=\mathrm{0.3214.}$ So the model predicts P3 draws about 32.1% of P1's dynamic power. (The table's listed 22 W vs 65 W = 33.8% is close — the small gap is leakage plus rounding.)

P0: $t=\frac{6\times 10^{11}}{4.0\times 10^9}=150\text{ s}$, $E=95\times 150=14250\text{ J}$. P2: $t=\frac{6\times 10^{11}}{2.8\times 10^9}=214.3\text{ s}$, $E=40\times 214.3=8571\text{ J}$. Savings: $\frac{14250-8571}{14250}=39.9\%$ energy, at the cost of $214.3-150=64.3$ s ($42.9\%$) more time.

A: $P_A=C_{\text{eff}}{V}^2(0.5f)=0.5P$. → 50% of original. B: $P_B=C_{\text{eff}}(0.7V{)}^2(0.5f)=0.49\cdot 0.5P=0.245P$. → 24.5% of original. Analysis: B burns less than half what A burns, for the same clock speed, purely from the $V^2$ term. This is the difference between DFS and DVFS.

$f_{\min }=\frac{N}{t_{\text{deadline}}}=\frac{5\times 10^6}{1\times 10^{-3}}=5\times 10^9=5\text{ GHz}.$ This exceeds the 4.0 GHz max — the task as written cannot meet its deadline at any P-state. You must cut $N$ (optimize the code) below $4\times 10^6$ cycles. See Real-time systems and CPU scheduling: for hard deadlines, DVFS may not scale down below the deadline floor.

Set $C_{\text{eff}}{V}^{2}f=V{I}_{\text{leak}}$: $f=\frac{V{I}_{\text{leak}}}{C_{\text{eff}}{V}^2}=\frac{I_{\text{leak}}}{C_{\text{eff}}V}=\frac{2}{(1\times 10^{-9})(1.0)}=2\times 10^9=2\text{ GHz}.$ Below 2 GHz, leakage dominates; above it, switching dominates. Crawling below 2 GHz wastes energy on leakage.

First $V(f)$: at 1 GHz, $V=0.25$; at 2 GHz, $V=0.50$; at 4 GHz, $V=1.0$. Time $t=N/f$. Energy $E=P(f)\cdot t=(C_{\text{eff}}{V}^{2}f+V{I}_{\text{leak}})\frac{N}{f}$.

1 GHz: $P=10^{-9}(0.25{)}^2(10^9)+0.25(0.5)=0.0625+0.125=0.1875\text{ W}$; $t=4\text{ s}$; $E=0.75\text{ J}$. 2 GHz: $P=10^{-9}(0.5{)}^2(2\times 10^9)+0.5(0.5)=0.5+0.25=0.75\text{ W}$; $t=2\text{ s}$; $E=1.5\text{ J}$. 4 GHz: $P=10^{-9}(1.0{)}^2(4\times 10^9)+1.0(0.5)=4+0.5=4.5\text{ W}$; $t=1\text{ s}$; $E=4.5\text{ J}$.

Best: 1 GHz at 0.75 J. Here leakage is small enough that slowing down still wins. Contrast with L4.2 where leakage is larger.

Leakage term $V{I}_{\text{leak}}$ is 6× bigger. 1 GHz: $P=0.0625+0.25(3)=0.0625+0.75=0.8125\text{ W}$; $t=4$; $E=3.25\text{ J}$. 2 GHz: $P=0.5+0.5(3)=0.5+1.5=2.0\text{ W}$; $t=2$; $E=4.0\text{ J}$. 4 GHz: $P=4+1.0(3)=4+3=7.0\text{ W}$; $t=1$; $E=7.0\text{ J}$. Best is still 1 GHz (3.25 J) — but notice the gap between 1 GHz and 4 GHz shrank from 6× (L4.1) to 2.2×. Push leakage higher and the answer flips to racing. This is the Race-to-idle vs race-to-dark tension, and why Power gating exists: cut leakage to zero by shutting the block off.

Coast: $t=2\times 10^9/10^9=2\text{ s}$ active, then idle at coast? Assume coast still runs the core the full window: but the job finishes at 2 s. To compare fairly over 4 s, coast finishes at 2 s then also sleeps. Active energy $=0.6\times 2=1.2\text{ J}$; sleep $0.05\times 2=0.1\text{ J}$; total $=1.3\text{ J}$. Race: $t=2\times 10^9/(4\times 10^9)=0.5\text{ s}$ active $=4.5\times 0.5=2.25\text{ J}$; sleep $3.5\text{ s}\times 0.05=0.175\text{ J}$; total $=2.425\text{ J}$. Coast wins here (1.3 J < 2.425 J) because racing's high $V^2$ active power dwarfs the leakage it avoids. Race-to-idle only wins when sleep saves more (very high leakage or high fixed platform power). See Thermal management: racing also spikes temperature.

(a) DVFS: 2 transitions per cycle (P0→P3 and P3→P0). Burst: $95\text{ W}\times 1\text{ ms}=95\text{ mJ}$. Idle: $22\text{ W}\times 4\text{ ms}=88\text{ mJ}$. Transitions: $2\times 20\mu \text{J}=0.04\text{ mJ}$. Total $=95+88+0.04=183.04\text{ mJ}$. (b) Stay P0: $95\text{ W}\times 5\text{ ms}=475\text{ mJ}$. DVFS saves $\frac{475-183.04}{475}=61.5\%$. The 0.04 mJ transition cost is negligible here because phases (ms) $\gg$ transition time (µs).

Each phase lasts $30\mu \text{s}$, but a single transition needs $\tau =50\mu \text{s}$ just to settle. The voltage cannot arrive before the phase is already over — DVFS cannot track this workload. Governor decision: do not switch. Pick one steady P-state (e.g. a mid P-state matching average demand), or use faster Power gating for the idle micro-gaps. The lesson: DVFS only helps when workload phases are much longer than the transition latency. Use Processor performance counters to measure phase length before deciding.

Ignoring leakage, energy = $C_{\text{eff}}{V}^{2}N$ and frequency cancels — so energy shrinks as $V$ (hence $f$) shrinks. Lower is always better for energy. The deadline stops us: we must have $t=N/f\le D$, i.e. $f\ge N/D$. $f_{\min }=\frac{3\times 10^9}{1.5}=2\times 10^9=2\text{ GHz}.$ So run at exactly 2 GHz — the slowest speed that still meets the deadline. Then $V=(2/4)(1.0)=0.5\text{ V}$ and $E=C_{\text{eff}}{V}^{2}N=10^{-9}(0.5{)}^2(3\times 10^9)=0.75\text{ J}.$ This is the classic result: stretch the job to exactly fill its deadline, no slower, no faster. (With leakage, the answer nudges up from the deadline floor — L4 style — because crawling too long leaks too much.)