Dynamic voltage and frequency scaling (DVFS): Question bank

True or false — justify

TF1. Halving only the frequency halves dynamic power.

True — dynamic power is linear in

f

, so

P = C_{eff} V^{2} f

drops to half. But it is a weak lever compared to voltage, which enters as

V^{2}

TF2. Halving only the frequency halves the energy used by a fixed-cycle task.

False — the task needs the same number of cycles

N

, so it just takes twice as long; energy

= C_{eff} V^{2} N

is unchanged because

V

never moved. Only lowering

V

saves energy on a fixed workload.

TF3. You can safely lower supply voltage while keeping frequency maxed out.

False — lower

V_{dd}

makes transistors charge their gates more slowly (delay

\propto V_{dd} / (V_{dd} - V_{t h})^{2}

), so logic may not settle before the next clock edge, causing timing errors. Voltage and frequency must drop together.

TF4. Running a compute-bound batch job at a lower P-state always saves energy.

False in general — it saves dynamic energy, but the job runs longer while static leakage keeps draining. On leaky deep-submicron nodes the extra leakage time can wipe out the dynamic savings (this is the race-to-idle argument, see Race-to-idle vs race-to-dark).

TF5. DVFS can meet any deadline as long as we pick a low enough P-state.

False — deadlines set a floor on frequency (

f_{min} = cycles / deadline

). If that floor exceeds the top P-state, no scaling helps; DVFS only uses headroom that Real-time systems leave above the deadline.

TF6. Because power scales with

V^{2}

, a 30% voltage cut alone gives ~51% power savings.

Misleading — you cannot cut voltage alone; the required frequency cut comes bundled (TF3). The real per-task saving comes from the combined move, and

V

and

f

are physically coupled by

f_{max} \propto (V_{dd} - V_{t h})^{α}

TF7. P-states are continuous — the controller can pick any voltage it wants.

False — P-states are a discrete, pre-validated set of

(V_{i}, f_{i})

pairs. Arbitrary combinations are not guaranteed stable, so hardware only exposes the tested rungs.

TF8. Frequency is changed by the same block that changes voltage.

False — frequency comes from the clock generator (PLL/FLL) while voltage comes from the voltage regulator. They are separate subsystems the power controller commands in the right order.

Spot the error

SE1. "Since

P = C_{eff} V^{2} f

, dropping

f

by half and

V

by half gives

\frac{1}{8}

the power."

The arithmetic is right (

\frac{1}{4} \cdot \frac{1}{2}

) but the premise is usually impossible — you rarely get to halve voltage for only a halved frequency, because

f_{max} \propto (V_{dd} - V_{t h})^{1.5 - 2}

ties them, and

V

cannot fall below what keeps logic above

V_{t h}

SE2. "Lowering voltage lowers leakage a lot, so idle chips barely leak."

Leakage

V \cdot I_{leak}

does fall with

V

, but

I_{leak}

itself stays substantial while the rails are powered — it only truly vanishes when you cut power entirely via Power gating, not by DVFS alone.

SE3. "A task that takes 25% longer at a lower P-state must cost 25% more energy."

Backwards — more time at lower voltage can cost less total energy; energy is power

\times

time, and the

V^{2}

drop in power outweighs the time increase, which is the whole point of scaling down.

SE4. "We should raise the clock first, then raise the voltage."

Wrong ordering when scaling up — you must raise voltage first so the transistors are fast enough, then raise frequency; do it the other way and the chip runs a clock its current voltage can't support, causing errors.

SE5. "DVFS is pure software — no hardware needed."

Wrong — software (the OS governor / CPU scheduling policy) decides, but a regulator, a PLL, and Processor performance counters to sense load are all required hardware.

SE6. "At 4.0 GHz the CPU always draws its rated 95 W."

Wrong — the 95 W is a worst-case at high activity factor

α

; actual dynamic power scales with how many gates actually switch, so a mostly-idle core at 4.0 GHz draws far less than its TDP.

Why questions

WHY1. Why is it "DVFS" and not just "DFS" (frequency scaling only)?

Because frequency alone gives only linear savings; the extra "V" unlocks the quadratic

V^{2}

term, which dominates the energy benefit. Scaling frequency exists to permit the voltage drop.

WHY2. Why does lowering voltage slow the transistors?

Drive current

\propto (V_{dd} - V_{t h})^{2}

, so lower

V_{dd}

means less current to charge each gate's capacitance, making delay

\propto V_{dd} / (V_{dd} - V_{t h})^{2}

grow — slower charging means logic settles later.

WHY3. Why does DVFS become less effective at very low frequencies?

Because static leakage power is roughly constant while dynamic power keeps shrinking, so leakage starts to dominate the total — pushing frequency ever lower buys almost nothing and just extends the leaking time.

WHY4. Why must DVFS cooperate with Thermal management?

Temperature is both an input (hot chips must scale down to shed heat) and a consequence (higher V/f makes more heat); the controller uses thermal sensors to cap the P-state and prevent emergency throttling.

WHY5. Why can't we just pick voltage from a formula on the fly instead of using discrete P-states?

Real silicon has process variation and stability margins, so each

(V, f)

pair must be validated in the lab; discrete tested rungs guarantee correctness where a computed value might sit in an unstable gap.

WHY6. Why do Processor performance counters matter for DVFS?

They measure real work (instructions, cache misses, utilization) so the controller can predict near-future demand — without them it would be guessing whether to scale up or down.

Edge cases

EC1. What happens when required frequency exceeds the top P-state?

DVFS is out of moves — you run at maximum P0 and must reduce the work (fewer cycles) instead, as in a hard real-time deadline that outstrips the fastest rung.

EC2. What is the energy behaviour as

f \to

very small but voltage is already floored at

\approx V_{t h}

Dynamic power keeps falling but voltage can't follow, so per-task dynamic energy plateaus while leakage energy grows with the longer runtime — total energy can start rising again, forming a sweet spot at an intermediate frequency.

EC3. What if the workload is bursty (mostly idle, brief spikes)?

Keep the average P-state low and jump to P0 only for spikes; because idle dominates the timeline and the

V^{2}

savings are large, average energy plummets even though peak power is high.

EC4. What if a task is memory-bound (waiting on RAM, not the CPU)?

The CPU stalls regardless of clock speed, so a high frequency wastes energy for little speedup — scaling down often costs almost no completion time while saving power, a classic DVFS win.

EC5. Zero activity factor (

α = 0

, no gates switching) — is dynamic power zero?

Yes, dynamic power vanishes since nothing charges or discharges, but static leakage

V \cdot I_{leak}

still flows while powered; only Power gating removes that residue.

EC6. Transition cost: is switching P-states free?

No — regulator and PLL transitions take ~10–100 μs, so thrashing between states can cost more time/energy than it saves; the governor must switch only when the benefit outlasts the transition overhead.

EC7. What is the theoretical floor for supply voltage in DVFS?

You cannot go below roughly the threshold voltage

V_{t h}

plus a safety margin, because at or under

V_{t h}

transistors barely conduct and logic no longer switches reliably.

Recall Quick self-test

Frequency-only scaling on a fixed task saves energy? ::: No — same cycles at same voltage means same energy, just more time. Which term makes DVFS lose effectiveness at ultra-low $f$ ? ::: Static leakage power, which stays roughly constant while dynamic power shrinks. Which subsystem changes $f$ vs $V$ ? ::: PLL/clock generator changes $f$ ; the voltage regulator changes $V$ .