Dynamic voltage and frequency scaling (DVFS): Exercises

6.4.2 · D4 · Hardware › Power, Thermal & Reliability › Dynamic voltage and frequency scaling (DVFS)

Recall Teen formulas jo aap har jagah reuse karenge

Dynamic power: $P_{dyn} = C_{eff} V^{2} f$ — energy per switch ( $\frac{1}{2} C V^{2}$ ) times switches per second ( $α f$ ). Static (leakage) power: $P_{leak} = V \cdot I_{leak}$ — woh current jo powered-on transistors mein trickle karta rehta hai, chahe kuch switch na ho. Fixed work $N$ cycles ke liye task energy: $E = P \cdot t$ jahan $t = N / f$ . Pure dynamic power ke liye yeh collapse hota hai $E_{dyn} = C_{eff} V^{2} N$ mein — frequency cancel ho jaati hai, isliye energy voltage par depend karti hai, speed par nahi (jab tak leakage ignore hai).

Is page par use hone wale symbols, ek baar defined:

Level 1 — Recognition

L1.1 — Quadratic term kaun sa hai?

$P_{dyn} = C_{eff} V^{2} f$ mein, agar aap sirf frequency double karein (voltage fixed), toh dynamic power ka kya hoga? Agar aap sirf voltage double karein (frequency fixed)?

Recall Solution

KYA: Exponents padho. $f$ power 1 par hai, $V$ power 2 par. $f$ double karo: $P \to C_{eff} V^{2} (2 f) = 2 P$ . Power double ho jaati hai (×2). $V$ double karo: $P \to C_{eff} (2 V)^{2} f = 4 C_{eff} V^{2} f = 4 P$ . Power chaar guna ho jaati hai (×4). YEH KYUN MATTER KARTA HAI: quadratic $V^{2}$ hi woh reason hai kyun DVFS voltage ko lower karta hai, sirf frequency ko nahi.

L1.2 — P-state table padho

Parent note ki Intel table use karte hue, kaun sa P-state sabse kam power deta hai, aur kaun sa sabse zyada frequency?

Recall Solution

Sabse kam power: P3 (0.90 V, 2.0 GHz, 22 W). Sabse zyada frequency: P0 (1.35 V, 4.0 GHz, 95 W). P0 "sprint" hai, P3 "coast" hai. Clock generation and PLs dekhein ki frequency actually kaise generate hoti hai, aur Voltage regulators dekhein ki voltage kaise deliver hoti hai.

L1.3 — Constraint ka naam batao

P3 ki frequency (2.0 GHz) ke saath P0 ki impossibly-low voltage (say 0.5 V) kyun set nahi kar sakte? Ek sentence mein.

Recall Solution

Kyunki lower voltage transistors ko slower switch karta hai ( $t_{delay} \propto V_{dd} / (V_{dd} - V_{t h})^{2}$ ), isliye kisi voltage ke neeche logic next clock edge se pehle finish nahi ho sakta — chip galat results deta hai. Voltage aur frequency ko saath-saath scale karna padta hai.

Level 2 — Application

L2.1 — Proportional scaling savings

Ek core $(V_{1}, f_{1})$ par run karta hai. Aap dono ko $k = 0.75$ se scale down karte ho. Dynamic power kitne fraction se girti hai? Task energy kitne fraction se girti hai (task = fixed $N$ cycles)?

Recall Solution

Power: $P_{2} = C_{eff} (k V_{1})^{2} (k f_{1}) = k^{3} P_{1} = 0.7 5^{3} P_{1} = 0.4219 P_{1}$ . Power $1 - 0.4219 = 57.8%$ girti hai. Energy: task $t_{2} = N / f_{2} = N / (k f_{1})$ leta hai, $1/ k$ se zyada lamba. Toh $E_{2} = P_{2} t_{2} = k^{3} P_{1} \cdot \frac{t _{1}}{k} = k^{2} E_{1} = 0.5625 E_{1}$ . Energy $1 - 0.5625 = 43.75%$ girti hai. DIFFERENCE KYUN: power $k^{3}$ se scale hoti hai ( $k$ ke teen factors), lekin energy ek factor $k$ wapas kho deti hai kyunki slower clock runtime stretch karta hai. Net: energy $\propto k^{2}$ .

L2.2 — Table mein plug karo

P1 (1.20 V, 3.5 GHz) se P3 (0.90 V, 2.0 GHz) move karo. Power ko pure dynamic maante hue ( $P = C_{eff} V^{2} f$ ), ratio $P_{P3} / P_{P1}$ kya hai?

Recall Solution

$\frac{P _{P3}}{P _{P1}} = \frac{V _{3}^{2} f _{3}}{V _{1}^{2} f _{1}} = \frac{0.9 0 ^{2} \cdot 2.0}{1.2 0 ^{2} \cdot 3.5} = \frac{0.81 \cdot 2.0}{1.44 \cdot 3.5} = \frac{1.62}{5.04} = 0.3214.$ Toh model predict karta hai ki P3, P1 ki dynamic power ka lagbhag 32.1% draw karta hai. (Table ka listed 22 W vs 65 W = 33.8% close hai — thoda gap leakage aur rounding ki wajah se hai.)

L2.3 — Fixed job ki energy

Ek task ko $N = 6 \times 1 0^{11}$ cycles chahiye. Isse P0 (4.0 GHz, 95 W) aur P2 (2.8 GHz, 40 W) par run karo. Dono ke liye time aur energy compute karo.

Recall Solution

P0: $t = \frac{6 \times 1 0 ^{11}}{4.0 \times 1 0 ^{9}} = 150 s$ , $E = 95 \times 150 = 14250 J$ . P2: $t = \frac{6 \times 1 0 ^{11}}{2.8 \times 1 0 ^{9}} = 214.3 s$ , $E = 40 \times 214.3 = 8571 J$ . Savings: $\frac{14250 - 8571}{14250} = 39.9%$ energy, $214.3 - 150 = 64.3$ s ( $42.9%$ ) zyada time ki cost par.

Figure — Dynamic voltage and frequency scaling (DVFS)

Level 3 — Analysis

L3.1 — Voltage-only vs voltage+frequency

Student A sirf frequency half karta hai: $f \to 0.5 f$ , $V$ fixed. Student B frequency half karta hai aur voltage $0.7 V$ par drop karta hai. Original ke fractions mein unki dynamic powers compare karo.

Recall Solution

A: $P_{A} = C_{eff} V^{2} (0.5 f) = 0.5 P$ . → original ka 50%. B: $P_{B} = C_{eff} (0.7 V)^{2} (0.5 f) = 0.49 \cdot 0.5 P = 0.245 P$ . → original ka 24.5%. Analysis: B, A se half se bhi kam burn karta hai, same clock speed ke liye, purely $V^{2}$ term ki wajah se. Yahi DFS aur DVFS ka fark hai.

L3.2 — Deadline floor

Ek control loop ko har $1 ms$ mein $N = 5 \times 1 0^{6}$ cycles run karne chahiye. Minimum frequency kya hai? Agar chip ka max 4.0 GHz hai, toh kya DVFS ka low P-state yahan usable hai?

Recall Solution

$f_{m i n} = \frac{N}{t _{deadline}} = \frac{5 \times 1 0 ^{6}}{1 \times 1 0 ^{- 3}} = 5 \times 1 0^{9} = 5 GHz .$ Yeh 4.0 GHz max se zyada hai — yeh task jaise likha hai, kisi bhi P-state par apna deadline meet nahi kar sakta. Aapko $N$ cut karna hoga (code optimize karo) $4 \times 1 0^{6}$ cycles se neeche. Real-time systems aur CPU scheduling dekhein: hard deadlines ke liye, DVFS deadline floor se neeche scale nahi kar sakta.

L3.3 — Dynamic aur static power kahan cross karte hain

Maano $P_{dyn} = C_{eff} V^{2} f$ aur $P_{leak} = V I_{leak}$ , with $C_{eff} = 1 nF$ , $I_{leak} = 2 A$ , aur $V = 1.0 V$ fixed. Kis frequency par dono powers ek doosre ke equal hoti hain?

Recall Solution

$C_{eff} V^{2} f = V I_{leak}$ set karo: $f = \frac{V I _{leak}}{C _{eff} V ^{2}} = \frac{I _{leak}}{C _{eff} V} = \frac{2}{( 1 \times 1 0 ^{- 9} ) ( 1.0 )} = 2 \times 1 0^{9} = 2 GHz .$ 2 GHz se neeche, leakage dominate karti hai; usse upar, switching dominate karti hai. 2 GHz se neeche crawling leakage par energy waste karta hai.

Level 4 — Synthesis

L4.1 — Total-energy sweet spot

Ek job ko $N = 4 \times 1 0^{9}$ cycles chahiye. Total power ko $P (f) = C_{eff} V^{2} f + V I_{leak}$ model karo jahan $V$ , $f$ ke saath linearly track karta hai: $V = f / f_{m a x} \cdot V_{m a x}$ with $f_{m a x} = 4 GHz$ , $V_{m a x} = 1.0 V$ . Use $C_{eff} = 1 nF$ , $I_{leak} = 0.5 A$ . $f = 1, 2, 4$ GHz par total energy compute karo aur batao kaun sa best hai.

Recall Solution

Pehle $V (f)$ : 1 GHz par, $V = 0.25$ ; 2 GHz par, $V = 0.50$ ; 4 GHz par, $V = 1.0$ . Time $t = N / f$ . Energy $E = P (f) \cdot t = (C_{eff} V^{2} f + V I_{leak}) \frac{N}{f}$ .

1 GHz: $P = 1 0^{- 9} (0.25)^{2} (1 0^{9}) + 0.25 (0.5) = 0.0625 + 0.125 = 0.1875 W$ ; $t = 4 s$ ; $E = 0.75 J$ . 2 GHz: $P = 1 0^{- 9} (0.5)^{2} (2 \times 1 0^{9}) + 0.5 (0.5) = 0.5 + 0.25 = 0.75 W$ ; $t = 2 s$ ; $E = 1.5 J$ . 4 GHz: $P = 1 0^{- 9} (1.0)^{2} (4 \times 1 0^{9}) + 1.0 (0.5) = 4 + 0.5 = 4.5 W$ ; $t = 1 s$ ; $E = 4.5 J$ .

Best: 1 GHz at 0.75 J. Yahan leakage itni chhoti hai ki slow karna abhi bhi jeet jaata hai. L4.2 se contrast karo jahan leakage badi hai.

L4.2 — Jab leakage answer flip kar deti hai

Same setup L4.1 jaisa lekin ek leaky deep-submicron chip ke saath: $I_{leak} = 3 A$ . 1, 2, 4 GHz par energy recompute karo. Ab kaun jeetता hai?

Recall Solution

Leakage term $V I_{leak}$ 6× badi hai. 1 GHz: $P = 0.0625 + 0.25 (3) = 0.0625 + 0.75 = 0.8125 W$ ; $t = 4$ ; $E = 3.25 J$ . 2 GHz: $P = 0.5 + 0.5 (3) = 0.5 + 1.5 = 2.0 W$ ; $t = 2$ ; $E = 4.0 J$ . 4 GHz: $P = 4 + 1.0 (3) = 4 + 3 = 7.0 W$ ; $t = 1$ ; $E = 7.0 J$ . Best abhi bhi 1 GHz hai (3.25 J) — lekin notice karo ki 1 GHz aur 4 GHz ka gap L4.1 ke 6× se shrink hokar 2.2× ho gaya. Leakage aur badhaao aur answer flip hokar racing mein aa jaayega. Yahi Race-to-idle vs race-to-dark tension hai, aur isliye Power gating exist karta hai: block band karke leakage ko zero pe cut karo.

L4.3 — Race-to-idle with sleep

Ek job ko $N = 2 \times 1 0^{9}$ cycles chahiye. Coast: hamesha 1 GHz par run karo (active power 0.6 W). Race-to-idle: 4 GHz par run karo (active power 4.5 W), jaldi khatam karo, phir sleep state mein drop ho jaao jo 0.05 W draw karta hai. Fixed 4-second window par total energy compare karo.

Recall Solution

Coast: $t = 2 \times 1 0^{9} /1 0^{9} = 2 s$ active, phir idle. 4 s fairly compare karne ke liye, coast 2 s par finish karta hai phir bhi sleep karta hai. Active energy $= 0.6 \times 2 = 1.2 J$ ; sleep $0.05 \times 2 = 0.1 J$ ; total $= 1.3 J$ . Race: $t = 2 \times 1 0^{9} / (4 \times 1 0^{9}) = 0.5 s$ active $= 4.5 \times 0.5 = 2.25 J$ ; sleep $3.5 s \times 0.05 = 0.175 J$ ; total $= 2.425 J$ . Coast yahan jeetta hai (1.3 J < 2.425 J) kyunki racing ka high $V^{2}$ active power leakage se bada hai jo woh avoid karta hai. Race-to-idle sirf tab jeetta hai jab sleep zyada save kare (bahut high leakage ya high fixed platform power). Thermal management dekhein: racing temperature bhi spike karta hai.

Level 5 — Mastery

L5.1 — Transition cost schedule badal deta hai

P-states switch karna free nahi hai: voltage regulator $τ = 50 μ s$ leta hai aur har transition par $E_{sw} = 20 μ J$ burn karta hai (dekhein Voltage regulators, Clock generation and PLs). Ek workload 1 ms bursts (P0 chahiye, 95 W) aur 4 ms idles (P3, 22 W) ke beech alternate karta hai. Ek poore 5 ms burst+idle cycle par compare karo (a) DVFS har phase switch karta hai vs (b) poori time P0 par rehta hai.

Recall Solution

(a) DVFS: cycle per 2 transitions (P0→P3 aur P3→P0). Burst: $95 W \times 1 ms = 95 mJ$ . Idle: $22 W \times 4 ms = 88 mJ$ . Transitions: $2 \times 20 μ J = 0.04 mJ$ . Total $= 95 + 88 + 0.04 = 183.04 mJ$ . (b) P0 par raho: $95 W \times 5 ms = 475 mJ$ . DVFS saves $\frac{475 - 183.04}{475} = 61.5%$ . 0.04 mJ transition cost yahan negligible hai kyunki phases (ms) $≫$ transition time (µs).

L5.2 — Jab transitions dominate karte hain

Ab workload har millisecond ki jagah har $30 μ s$ mein flip karta hai. Same $τ = 50 μ s$ , $E_{sw} = 20 μ J$ . Kya DVFS yahan physically possible hai? Governor ko kya karna chahiye?

Recall Solution

Har phase $30 μ s$ chalta hai, lekin ek transition ko settle hone ke liye akele $τ = 50 μ s$ chahiye. Voltage phase khatam hone se pehle aa hi nahi sakta — DVFS is workload ko track nahi kar sakta. Governor decision: switch mat karo. Ek steady P-state choose karo (jaise average demand ke match karne wala ek mid P-state), ya idle micro-gaps ke liye faster Power gating use karo. Lesson: DVFS tabhi help karta hai jab workload phases transition latency se bahut lambe hon. Switch karne ka decide karne se pehle phase length measure karne ke liye Processor performance counters use karo.

L5.3 — Full optimization: deadline ke under energy minimize karo

Ek job ko $N = 3 \times 1 0^{9}$ cycles chahiye aur deadline $D = 1.5 s$ ke andar finish hona chahiye. Power model $P (f) = C_{eff} V^{2} f$ with $V = f / f_{m a x} \cdot V_{m a x}$ , $f_{m a x} = 4 GHz$ , $V_{m a x} = 1.0 V$ , $C_{eff} = 1 nF$ (leakage ignore karo). Kaun si single frequency energy minimize karti hai aur deadline bhi meet karti hai?

Recall Solution

Leakage ignore karne par, energy = $C_{eff} V^{2} N$ aur frequency cancel ho jaati hai — toh energy $V$ (hence $f$ ) ke ghattne par shrink hoti hai. Energy ke liye lower hamesha better hai. Deadline hume rokti hai: $t = N / f \leq D$ hona chahiye, yaani $f \geq N / D$ . $f_{m i n} = \frac{3 \times 1 0 ^{9}}{1.5} = 2 \times 1 0^{9} = 2 GHz .$ Toh exactly 2 GHz par run karo — woh sabse slow speed jo deadline abhi bhi meet karti hai. Phir $V = (2/4) (1.0) = 0.5 V$ aur $E = C_{eff} V^{2} N = 1 0^{- 9} (0.5)^{2} (3 \times 1 0^{9}) = 0.75 J .$ Yahi classic result hai: job ko exactly apna deadline fill karne tak stretch karo, na slower, na faster. (Leakage ke saath, answer deadline floor se upar nudge karta hai — L4 style — kyunki bahut zyada crawling bhi bahut zyada leak karta hai.)

Self-test recall

Right side cover karo aur answer do:

Sirf voltage double karne par dynamic power kitne se multiply hoti hai

4 (the

V^{2}

term)

Dono

V

aur

f

ka proportional

k

-scaling task energy ko multiply karta hai

k^{2}

N

cycles ke liye time

D

mein deadline floor frequency

f_{m i n} = N / D

Dynamic-vs-leakage crossover frequency se neeche, dominant power hoti hai

static leakage

V I_{leak}

DVFS switching tabhi help karti hai jab workload phases hoon

transition latency

τ

se bahut lambe