Exercises — System-on-Chip (SoC) integration

A master issues read/write requests on its own initiative; a slave only ever answers a request aimed at its address range.

• (a) CPU — master (fetches instructions, reads/writes data).
• (b) DDR controller — slave (it is targeted by an address; it responds).
• (c) DMA engine — master (it moves data by issuing its own reads/writes — that is the whole point of DMA).
• (d) UART registers — slave (the CPU pokes its config registers).

Answer: master = a, c ; slave = b, d.

From the AMBA Bus Standards family: $\text{AXI}>\text{AHB}>\text{APB}$

• AXI — high performance, supports out-of-order, burst, separate read/write channels.
• AHB — mid-tier shared bus.
• APB — simplest, low-speed, ideal for peripheral registers like the UART.

WHAT we do: plug into the formula. WHY the $\min$: at most one transfer can enter each slave port per cycle, and at most one can leave each master port — so the number of simultaneous transfers is capped by whichever side has fewer ports. $\min (4,3)=3\Rightarrow B_{\text{total}}=3\times 4=\boxed{12\text{GB/s}}.$ See the figure below — three coloured paths run in parallel, the 4th master must wait.

(a) An AXI-to-APB bridge — it translates AXI's channelled protocol into APB's simple enable/select handshake. Without it the two protocols never agree and the bus hangs. (b) A 4 KB window means the low 12 bits ($2^{12}=4096$) are the offset inside the peripheral, so the decoder inspects address[31:12]: $\text{if address[31:12] == 0x40000 then route to APB bridge.}$ Careful: 0x4000_0000 >> 12 = 0x40000 (5 hex digits), not 0x4000.

$\text{divider}=\frac{1000\text{MHz}}{50\text{MHz}}=20.$ So uart_clk = cpu_clk / 20. Because 1 GHz and 50 MHz are effectively asynchronous domains, every control signal crossing needs a CDC synchroniser (see Clock Domain Crossing Techniques) — a two-flop synchroniser for single-bit signals.

A slave has one port. If everyone wants DRAM, transactions serialise through that single port: $B_{\text{worst}}=1\times B=4\text{GB/s}.$ Drop factor vs. best case: $\frac{B_{\text{total}}}{B_{\text{worst}}}=\frac{12}{4}=3\times .$ Lesson: the crossbar didn't get slower — the access pattern collapsed the parallelism. This is why hot-spot slaves (DRAM) often get multiple ports / banks.

Why it breaks: each bit's synchroniser resolves metastability independently. On any given crossing cycle some bits may have settled and some may still be resolving, so the 32-bit word the receiver latches is a mix of old and new bits — a value that never existed. This is bit skew, and it is invisible on single-bit signals. Correct fixes: (i) a handshake — hold the 32-bit data static while a synchronised valid pulse tells the receiver "sample now, all bits are stable"; or (ii) an async FIFO using Gray-coded pointers (only one pointer bit changes per step, so the pointer itself is safe to synchronise). See Clock Domain Crossing Techniques.

Baseline (never gated): idle 90% at 2 W, active 10% at 10 W: $P_{\text{base}}=0.9(2)+0.1(10)=1.8+1.0=2.8\text{W}.$ Gated: during idle the domain is fully off (0 W); active period unchanged: $P_{\text{gated}}=0.9(0)+0.1(10)=1.0\text{W}.$ Average saved: $P_{\text{saved}}=2.8-1.0=1.8\text{W}.$ This matches the parent note's shortcut $0.9\times 2=1.8$ W, because we saved exactly the idle-leakage term. See Power Management in SoCs.

Walk the four integration axes from the parent note:

1. Interconnect: ISP is an AXI master → wire it as a new master port on the AXI crossbar; assign DRAM (its target) an address range in the decoder. Prevents: protocol mismatch / mis-routing.
2. Power domain plumbing (Power Management in SoCs):
   • Power switches gated by the PMU (turn the ISP domain on/off).
   • Isolation cells clamp ISP outputs to a known value while it is off. Prevents: floating outputs leaking current into live neighbours.
   • Level shifters if the ISP runs at a different voltage than the AXI fabric. Prevents: a low-domain "high" not registering as high in the higher-voltage domain.
   • Retention flops (on an always-on rail) for any config registers that must survive power-down. Prevents: losing configuration on wake.
3. Clock Domain Crossing (Clock Domain Crossing Techniques): 400 MHz ↔ 1.2 GHz are asynchronous. The AXI stream crossing needs an async AXI bridge / async FIFO (multi-bit → handshake, not raw two-flop). Prevents: metastability and 32-bit bit-skew.
4. Interrupt wiring: connect isp_irq (frame-done) to a free interrupt-controller input so the CPU is notified. Prevents: CPU polling / missed frames.

$d=\frac{1200\text{MHz}}{400\text{MHz}}=3.$ Even with an exact integer divide, the divided clock's edges are generated by a separate PLL/divider path with its own phase and jitter; the tool treats them as asynchronous unless the entire clock tree is provably phase-locked, so CDC synchronisers are still mandatory across the boundary.

(a) With 16 masters we are past the crossbar sweet spot (3–8). Choose a Network-on-Chip (Network-on-Chip (NoC)) — packet-switched routers scale to 100+ cores. (b) Crossbar area grows as the full connectivity matrix: $A_{\text{xbar}}\propto M\times N=16\times 16=256\text{switch-cells}.$ A shared bus is $\propto 1$ wire-bundle but serialises everyone → useless bandwidth at 16 masters. A NoC spends area on routers that grows roughly linearly ($\propto$ number of nodes) while still allowing many simultaneous packet flows. So: $\underset{\text{crossbar}}{\underbrace{256}}\gg \underset{\text{NoC routers}}{\underbrace{\approx 16}}$ the crossbar's quadratic blow-up is what makes it uneconomical here, while the shared bus's single serial path throttles throughput. NoC is the only option that scales in both area and bandwidth.

$A_4\propto 4\times 4=16,A_{16}\propto 16\times 16=256.$ $\text{growth factor}=\frac{256}{16}=16\times .$ Doubling both dimensions quadruples cells; a $4\times$ increase in each dimension gives a $16\times$ increase overall. Rule: area scales as the product $M\times N$ (quadratic when $M=N$), so every doubling of node count multiplies fabric cost by $\sim 4$. That superlinear cost is exactly why the industry switches from crossbars to packet-switched NoCs (linear-ish scaling) past a handful of masters.

Crossbar best case ::: $\min (4,3)\times 4=12$ GB/s Crossbar worst case (shared slave) ::: $1\times 4=4$ GB/s, a $3\times$ drop UART divider (1 GHz → 50 MHz) ::: 20 ISP divider (1.2 GHz → 400 MHz) ::: 3 Decode bits for a 4 KB window ::: top 20 bits, address[31:12] == 0x40000 GPU power-gating average saving ::: 1.8 W Crossbar area 4×4 → 16×16 ::: 16 → 256 cells, $16\times$ growth