6.3.9 · D5Interconnects, Buses & SoC
Question bank — System-on-Chip (SoC) integration
This is a rapid-fire trap sweep for System-on-Chip (SoC) integration. Each line is a Question ::: Answer reveal. Read the question, commit to an answer out loud, then reveal. If your gut answer was "yes/no" with no reason, you failed the item — the reasoning is the point.
Every trap below targets a specific misconception or boundary case that SoC integration deliberately sets up. Related deep topics: AXI Protocol, Clock Domain Crossing Techniques, Power Management in SoCs, Network-on-Chip (NoC), AMBA Bus Standards, Physical Design Flow, Formal Verification Methods.
True or false — justify
A two-flop synchronizer is the two-register chain that lets a signal cross safely between clock domains; metastability is a flop output stuck between valid 0 and 1 for an unpredictable time after a setup/hold violation.
A two-flop synchronizer makes metastability impossible
False — it only makes it exponentially unlikely. The first flop can still go metastable; the second flop just grants a full clock period for it to resolve, pushing MTBF up but never to infinity.
You can safely run a 32-bit data bus through 32 parallel two-flop synchronizers
False — each bit resolves on a possibly different cycle, so the receiver can latch a mix of old and new bits (a value that was never sent). Multi-bit crossings need a handshake or a Gray-coded async FIFO.
Putting everything on one die always lowers total power
Mostly true in practice but not automatically — you remove power-hungry off-chip drivers, yet on-die you now pay for leakage in every always-on block and thermal throttling from hotspots. The saving is real but conditional on good power-domain management.
An AXI-to-APB bridge is optional if the UART "kind of works" without it
False — the bridge translates protocol, not speed. Without it the AXI master issues handshakes the APB slave never acknowledges, so the transaction never completes and the bus hangs.
Isolation cells and level shifters do the same job
False — an isolation cell clamps a powered-down domain's floating output to a known 0/1; a level shifter retranslates a valid signal between two different voltages. One handles "the source is dead", the other handles "the source speaks a different voltage".
Crossbar total bandwidth is always for masters
False — it is . If there are fewer slave ports than masters, the slave side is the bottleneck, and if all masters hit one slave it collapses to a single .
Retention registers keep their value because they're powered by the same domain
False — that's the contradiction. A powered-down domain loses its flop state; retention flops keep a shadow copy powered by a separate always-on rail.
Gray coding is used in async FIFO pointers because it's faster to compute
False — it's used because only one bit changes per increment, so even if the crossing catches a mid-transition value, it can only be the old or new pointer, never a corrupt in-between count.
Spot the error
Each item states a plan a designer might write. Find what breaks.
"UART at 0x4000_0000–0x4000_0FFF, GPIO at 0x4000_0800–0x4000_0FFF, done."
The two ranges overlap (both include 0x4000_0800+). The decoder can't uniquely route those addresses, so reads/writes hit the wrong or both peripherals — a classic address-map collision.
"CPU at 1 GHz, UART at 50 MHz, so I set uart_clk = cpu_clk / 20 and wire the IRQ straight over."
The divided clock is fine, but the control/status signals now cross an asynchronous domain boundary. The raw IRQ wire needs a synchronizer; wiring it straight risks metastability on the interrupt controller input.
"Domain A is 1.2 V, Domain B is 0.9 V; B drives A directly since 0.9 V still reads as logic high."
0.9 V may fall below A's input-high threshold, so A can read it as a weak/undefined level, causing crowbar current and unreliable logic. A level shifter up to 1.2 V is required for B→A signals.
"I'll power-gate the GPU; the outputs it leaves floating are harmless."
Floating outputs from the dead domain can drift to mid-rail and inject leakage/shoot-through current into live neighbours. Isolation cells must clamp them before the domain powers off.
"32 masters, 4 slaves, so my crossbar area is fine — bandwidth scales with masters."
Crossbar area/power grows as (here 128 crosspoints) and usable bandwidth is capped at , not . At this master count a Network-on-Chip (NoC) is the scalable choice.
"Soft IP is already silicon-proven, so I can drop it in without re-verification."
Soft IP is RTL — it must still be synthesized, timing-closed, and verified in your context (clocking, constraints, corners). Only hard IP carries a tested physical layout, and even that needs integration checks.
"Best case, all 4 masters hit DRAM, so I get ."
All hitting one slave is the worst case — they serialize through DRAM's single port for . Best case is each master hitting a different slave.
Why questions
Why does MTBF against metastability improve exponentially with added wait time, not linearly?
Metastable resolution is an exponential decay (): each extra unit of settle time multiplies (not adds to) the odds the flop has resolved, so a small delay increase buys a huge reliability gain.
Why insert an AXI-to-APB bridge instead of just redesigning the UART to speak AXI?
The UART is reused IP — rewriting its interface throws away its proven, silicon-tested value and adds risk. A bridge is a small, reusable adapter that preserves the block as-is.
Why do SoCs use multiple clock domains at all instead of one global clock?
A UART generating baud rates needs a slow clock while the CPU needs a fast one; forcing everything to one frequency wastes power on slow blocks and makes global clock distribution/skew across a huge die nearly impossible.
Why can't the crossbar just give infinite bandwidth by adding ports?
Two masters targeting the same slave must serialize through that slave's single port regardless of crossbar width — real throughput is set by access patterns and arbitration, not port count.
Why separate power domains rather than a single power-gate for the whole idle chip?
Different blocks are idle at different times (camera off, CPU busy); one global gate would force everything off together. Independent domains let you shut only the truly-idle block while the rest keeps running.
Why does dynamic power scale with but leakage still matters when a block is "just idle"?
drops toward zero when switching stops (), but static leakage flows whenever the block is merely powered — that's why an idle GPU can still burn 2 W and why you power-gate, not just clock-gate, to kill it.
Edge cases
What happens to a two-flop synchronizer if the source signal toggles faster than the destination clock?
Pulses can be missed entirely (the destination samples between edges) or seen once instead of many times. Fast toggling data needs a handshake/FIFO with flow control, not a bare synchronizer.
What is the crossbar bandwidth when but only one master is active?
Just — a single master can drive at most one link at a time. The ceiling is only reached with multiple masters hitting distinct slaves concurrently.
What happens on power-up ordering if a live domain drives into a not-yet-powered domain?
The unpowered domain's inputs can be back-driven, forwarding current through protection diodes and possibly latching up. Power sequencing plus isolation must guarantee the receiver is ready before signals arrive.
Degenerate case: a "clock domain crossing" where source and destination clocks are actually the same net — is a synchronizer needed?
No — if the clocks are genuinely identical (same source, phase-related), there's no asynchronous relationship, and adding a synchronizer only wastes a cycle of latency. CDC hardware is for asynchronous or unrelated clocks.
Zero-activity boundary: what is for a domain that is clock-gated but still powered?
and effective go to ~0 so dynamic power vanishes, but static leakage remains because voltage is still applied — only power-gating removes that residual draw.
What if two IP blocks both expect to be bus master at the same address?
The interconnect must arbitrate; without defined arbitration priority they can deadlock or one starves indefinitely. Master conflicts are resolved by the fabric's arbitration policy, not by the address map (which resolves slaves).
Recall Fast self-test
Name the four hidden agreements two IP blocks must share to integrate. ::: Protocol (bus handshake), clocking (domain/synchronization), power (rails, isolation, level shift), and address map (unique, non-overlapping ranges).