Exercises — System-on-Chip (SoC) integration

Ek master apni marzi se read/write requests bhejta hai; ek slave sirf tab jawab deta hai jab uske address range par koi request aaye।

• (a) CPU — master (instructions fetch karta hai, data read/write karta hai)।
• (b) DDR controller — slave (ise ek address se target kiya jaata hai; yeh respond karta hai)।
• (c) DMA engine — master (yeh data move karta hai apne khud ke reads/writes issue karke — DMA ka poora maqsad yehi hai)।
• (d) UART registers — slave (CPU iski config registers ko poke karta hai)।

Jawab: master = a, c ; slave = b, d।

AMBA Bus Standards family se: $\text{AXI}>\text{AHB}>\text{APB}$

• AXI — high performance, out-of-order, burst, aur separate read/write channels support karta hai।
• AHB — mid-tier shared bus।
• APB — sabse simple, low-speed, UART jaise peripheral registers ke liye ideal।

KYA karna hai: formula mein plug karo। KYUN $\min$ hai: zyada se zyada ek transfer har slave port mein enter ho sakti hai per cycle, aur zyada se zyada ek har master port se nikal sakti hai — isliye simultaneous transfers ki sankhya us side se cap hoti hai jiske paas kam ports hain। $\min (4,3)=3\Rightarrow B_{\text{total}}=3\times 4=\boxed{12\text{GB/s}}.$ Neeche diye figure mein dekho — teen coloured paths parallel mein run karte hain, 4th master ko wait karna padta hai।

(a) Ek AXI-to-APB bridge — yeh AXI ke channelled protocol ko APB ke simple enable/select handshake mein translate karta hai। Iske bina dono protocols kabhi agree nahi karte aur bus hang ho jaata hai। (b) 4 KB window ka matlab hai ki neeche ke 12 bits ($2^{12}=4096$) peripheral ke andar ka offset hain, isliye decoder address[31:12] inspect karta hai: $\text{if address[31:12] == 0x40000 then route to APB bridge.}$ Dhyan raho: 0x4000_0000 >> 12 = 0x40000 (5 hex digits) hai, 0x4000 nahi।

$\text{divider}=\frac{1000\text{MHz}}{50\text{MHz}}=20.$ Toh uart_clk = cpu_clk / 20। Kyunki 1 GHz aur 50 MHz effectively asynchronous domains hain, har control signal crossing ko ek CDC synchroniser chahiye (dekho Clock Domain Crossing Techniques) — single-bit signals ke liye ek two-flop synchroniser।

Ek slave ka ek port hota hai। Agar sab DRAM chahte hain, toh transactions us single port se serialise ho jaate hain: $B_{\text{worst}}=1\times B=4\text{GB/s}.$ Best case ke mukable drop factor: $\frac{B_{\text{total}}}{B_{\text{worst}}}=\frac{12}{4}=3\times .$ Lesson: crossbar slow nahi hua — access pattern ne parallelism collapse kar di। Isliye hot-spot slaves (DRAM) ko often multiple ports / banks milte hain।

Kyun toot ta hai: har bit ka synchroniser metastability independently resolve karta hai। Kisi bhi given crossing cycle par kuch bits settle ho chuki ho sakti hain aur kuch abhi bhi resolve ho rahi ho sakti hain, isliye receiver jo 32-bit word latch karta hai woh purane aur naye bits ka mix hota hai — ek aisi value jo kabhi exist hi nahi ki। Yeh bit skew hai, aur single-bit signals par yeh dikhayi nahi deta। Correct fixes: (i) ek handshake — 32-bit data ko static rakho jabki ek synchronised valid pulse receiver ko bataye "ab sample karo, saare bits stable hain"; ya (ii) ek async FIFO jo Gray-coded pointers use kare (har step par sirf ek pointer bit badalta hai, isliye pointer khud synchronise karna safe hai)। Dekho Clock Domain Crossing Techniques।

Baseline (kabhi gate nahi): idle 90% at 2 W, active 10% at 10 W: $P_{\text{base}}=0.9(2)+0.1(10)=1.8+1.0=2.8\text{W}.$ Gated: idle mein domain fully off hai (0 W); active period unchanged: $P_{\text{gated}}=0.9(0)+0.1(10)=1.0\text{W}.$ Average saved: $P_{\text{saved}}=2.8-1.0=1.8\text{W}.$ Yeh parent note ke shortcut $0.9\times 2=1.8$ W se match karta hai, kyunki humne exactly idle-leakage term bachaya। Dekho Power Management in SoCs।

Parent note ke chaar integration axes par chalo:

1. Interconnect: ISP ek AXI master hai → ise AXI crossbar par ek naye master port ke roop mein wire karo; decoder mein DRAM (iska target) ko ek address range assign karo। Rokta hai: protocol mismatch / mis-routing।
2. Power domain plumbing (Power Management in SoCs):
   • Power switches jo PMU se gate hote hain (ISP domain ko on/off karte hain)।
   • Isolation cells ISP outputs ko ek known value par clamp karti hain jab woh off ho। Rokta hai: floating outputs se live neighbours mein current leak होना।
   • Level shifters agar ISP AXI fabric se alag voltage par run karta ho। Rokta hai: low-domain "high" ka higher-voltage domain mein high register na होना।
   • Retention flops (hamesha-on rail par) kisi bhi config registers ke liye jo power-down survive karne chahiye। Rokta hai: wake par configuration kho देना।
3. Clock Domain Crossing (Clock Domain Crossing Techniques): 400 MHz ↔ 1.2 GHz asynchronous hain। AXI stream crossing ko ek async AXI bridge / async FIFO chahiye (multi-bit → handshake, raw two-flop nahi)। Rokta hai: metastability aur 32-bit bit-skew।
4. Interrupt wiring: isp_irq (frame-done) ko ek free interrupt-controller input se connect karo taaki CPU ko notify ho। Rokta hai: CPU polling / missed frames।

$d=\frac{1200\text{MHz}}{400\text{MHz}}=3.$ Exact integer divide ke baad bhi, divided clock ke edges ek alag PLL/divider path se apne khud ke phase aur jitter ke saath generate hote hain; tool inhe asynchronous treat karta hai jab tak poora clock tree provably phase-locked na ho, isliye boundary par CDC synchronisers abhi bhi mandatory hain।

(a) 16 masters ke saath hum crossbar sweet spot (3–8) se aage nikal gaye hain। Network-on-Chip (Network-on-Chip (NoC)) choose karo — packet-switched routers 100+ cores tak scale karte hain। (b) Crossbar area full connectivity matrix ki tarah badhti hai: $A_{\text{xbar}}\propto M\times N=16\times 16=256\text{switch-cells}.$ Ek shared bus $\propto 1$ wire-bundle hai lekin sab ko serialise karta hai → 16 masters par useless bandwidth। Ek NoC routers par area spend karta hai jo roughly linearly badhta hai ($\propto$ nodes ki sankhya) jabki abhi bhi kai simultaneous packet flows allow karta hai। Toh: $\underset{\text{crossbar}}{\underbrace{256}}\gg \underset{\text{NoC routers}}{\underbrace{\approx 16}}$ crossbar ka quadratic blow-up hi use yahan uneconomical banata hai, jabki shared bus ka single serial path throughput throttle karta hai। NoC ek hi option hai jo dono area aur bandwidth mein scale karta hai।

$A_4\propto 4\times 4=16,A_{16}\propto 16\times 16=256.$ $\text{growth factor}=\frac{256}{16}=16\times .$ Dono dimensions double karne par cells quadruple ho jaate hain; har dimension mein $4\times$ increase se overall $16\times$ increase hota hai। Rule: area product $M\times N$ ki tarah scale karta hai (quadratic jab $M=N$), isliye node count har doubling se fabric cost ko $\sim 4$ se multiply kar deti hai। Yahi superlinear cost theek woh reason hai jis wajah se industry kuch masters ke baad crossbars se packet-switched NoCs (linear-ish scaling) par switch karti hai।

Crossbar best case ::: $\min (4,3)\times 4=12$ GB/s Crossbar worst case (shared slave) ::: $1\times 4=4$ GB/s, ek $3\times$ drop UART divider (1 GHz → 50 MHz) ::: 20 ISP divider (1.2 GHz → 400 MHz) ::: 3 Decode bits for a 4 KB window ::: top 20 bits, address[31:12] == 0x40000 GPU power-gating average saving ::: 1.8 W Crossbar area 4×4 → 16×16 ::: 16 → 256 cells, $16\times$ growth