Visual walkthrough — Pipeline registers and control signals

5.2.4 · D2 · Hardware › Processor Datapath & Pipelining › Pipeline registers and control signals

Hum single-cycle picture se shuru karte hain (dekho Single-cycle datapath) aur dheere dheere discover karte hain kyun stages ke beech boxes aane chahiye, aur kya har box ke andar hona chahiye.

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Step 1 — Pehle, "register" kya hota hai? Ek box jo tick pe yaad rakhta hai

HUMNE KYA KIYA: humne ek hi building block ko naam diya jo humhein chahiye. Uske teen cheezein hain: input wires (left), output wires (right), aur ek clock tick (bottom).

KYUN CHAHIYE: combinational logic (adders, ALUs, muxes) ki koi memory nahi hoti — uska output turant change hota hai jaise hi uska input change hota hai. Agar do instructions ki values ek hi adder par overlapping times pe pahunche, toh woh blur ho jaati hain. Ek register ek value ko freeze karta hai taaki agla stage ek stable snapshot read kar sake. Tick ke baare mein dekho Clocking and edge-triggered flip-flops.

PICTURE: neeche ka box. Red wire woh value hai jo capture ho rahi hai; notice karo ki output sirf clock ke black tick marks par step karta hai nayi value tak — beech mein yeh flat rehta hai.

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Step 2 — Har ek pair of stages ke beech ek wall kyun zaroor honi chahiye

HUMNE KYA KIYA: hum Step 1 ka ek register (wall) har neighbouring stages ke gap par rakh dete hain.

KYUN: wall ke bina, jab EX instruction A finish karta hai aur instruction B shuru karta hai, B ki adhi-pakki value turant aage flood ho jaati hai aur A ki value ko overwrite kar deti hai isse pehle ki MEM ne use read kiya ho. Wall tick par A ka output latch karta hai, isliye MEM agale cycle mein A ko read karta hai jabki EX aazaadi se B ko process karta hai.

KYUN sirf 4 walls, 5 nahi: 5 stages hain lekin unke beech sirf 4 gaps hain. WB ke baad koi gap nahi hai — WB ka output seedha register file mein jaata hai, jo khud ek memory hai. 5th wall add karna sirf har write ko ek tick delay karta aur hazards ko worse banata (dekho Pipeline hazards).

PICTURE: paanch boxes (stages) ek row mein chaar red walls ke saath gaps mein. Gino: red walls hain IF/ID, ID/EX, EX/MEM, MEM/WB.

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Step 3 — EX/MEM wall ko kaun sa DATA carry karna chahiye? EX se bahar jaane wale arrows follow karo

Ab hum ek wall par zoom karte hain — EX/MEM, Execute aur Memory ke beech ki wall — aur iske contents scratch se derive karte hain. Rule bilkul simple hai:

Dekho kya kya Execute compute karta hai aur har cheez ke liye pucho: kya koi right side wala abhi bhi yeh chahta hai?

• ALU result (32 bits): loads/stores ke liye memory address ke roop mein chahiye, aur data write back karne ke liye bhi. → cross karni chahiye.
• Store data (32 bits): sw ke liye, memory mein likhi jaane wali value ID mein read hoti hai aur EX mein bina kuch kiye ride karti hai, MEM mein consume hoti hai. → cross karni chahiye.
• Branch target (32 bits): $PC+4+(\text{imm}\ll 2)$, EX mein ek adder se compute hota hai, agar branch liya gaya toh MEM mein use hota hai. → cross karni chahiye.
• Zero flag (1 bit): ALU ki "kya result zero tha?" line, MEM mein branch decide karne ke liye use hoti hai. → cross karni chahiye.

HUMNE KYA KIYA: data fields ki list banayi jo EX se bahar survive karti hain.

KYU HAR EK: har ek is wall ke upstream produce hoti hai, aur downstream consume hoti hai. Koi bhi drop karo aur baad wala stage chupchap garbage read karega.

PICTURE: EX se nikalne wale chaar data arrows, har ek par uski bit-width ka label; red arrow 32-bit ALU result hai, jo sabse important hai.

$\underset{\begin{array}{c}\text{ALU}\\ \text{result}\end{array}}{\underbrace{32}}+\underset{\begin{array}{c}\text{store}\\ \text{data}\end{array}}{\underbrace{32}}+\underset{\begin{array}{c}\text{branch}\\ \text{target}\end{array}}{\underbrace{32}}+\underset{\begin{array}{c}\text{Zero}\\ \text{flag}\end{array}}{\underbrace{1}}=97\text{ data bits so far}$

Upar har symbol ek wire count hai: "32" matlab ek 32-bit-wide value physically wall mein 32 flip-flops occupy karta hai.

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Step 4 — Ek chhupi hui cheez: destination register number bhi saath jaana chahiye

HUMNE KYA KIYA: humne ek 5-bit field — destination register number — wall mein add kiya.

KYUN 5 bits: MIPS mein $2^5=32$ registers hain, isliye ek register ka naam ek 5-bit number hota hai.

KYUN use travel karna padta hai: agar WB iske bajay "jo bhi register field abhi current instruction ki wires par hai" use padhe, toh woh galat register mein likhega. Yeh classic "pipelined ki jagah current instruction ka field use kar liya" datapath bug hai. Number ID/EX → EX/MEM → MEM/WB ke through latch hota hai, WB mein sahi, purani instruction se tagged hokar pahunchta hai.

PICTURE: 5-bit dest-# (red) teeno walls ke through ek luggage tag ki tarah thread ho raha hai, jabki instruction word (grey) ID ke baad discard ho jaata hai.

$97+\underset{\begin{array}{c}\text{dest}\\ \text{reg }\#\end{array}}{\underbrace{5}}=102\text{ bits (data + tag)}$

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Step 5 — Control signals: woh paperwork jo wall cross bhi karta hai

Har control signal ek baar, ID mein generate hoti hai, control unit ke opcode read karne se (dekho Control unit design). Lekin yeh alag alag times par use hoti hain. Parent ne inhe teen bundles mein group kiya tha based on kaun sa stage inhe consume karta hai:

Bundle	Signals	Bits	Consumed mein
EX	ALUSrc, ALUOp, RegDst	3	Execute
MEM	MemRead, MemWrite, Branch	3	Memory
WB	RegWrite, MemtoReg	2	Write-back

HUMNE KYA KIYA: humne find kiya ki kaun se bundles EX/MEM wall cross karne ki zaroorat hai.

KYUN sirf MEM + WB cross karte hain: jab tak hum EX/MEM wall tak pahunchte hain, EX apna bundle consume kar chuka hai — woh use ho gaya, isliye hum use drop karte hain. Sirf MEM bundle (agla use hoga) aur WB bundle (do stages baad use hoga) survive karte hain.

PICTURE: ID/EX mein enter hote teen bundles; EX bundle (grey) EX par gir jaata hai, aur red MEM+WB bundles EX/MEM mein continue karte hain.

$102+\underset{|MEM|}{\underbrace{3}}+\underset{|WB|}{\underbrace{2}}=107\text{ bits}=W_{EX/MEM}$

Yahan $|MEM|$ matlab "MEM bundle mein wires ki sankhya" $=3$ hai, aur $|WB|=2$. Yahi parent ka 107 hai. Humne ise wire by wire build kiya.

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Step 6 — Har wall, har case: har register kya carry karta hai aur kya drop karta hai

HUMNE KYA KIYA: humne Step 5 ko chaaon sari walls tak generalize kiya.

KYUN yeh important hai: yeh har case cover karta hai — koi wall mysterious nahi rehti.

• IF/ID: raw instruction word + PC+4 carry karta hai. Abhi tak koi control nahi — opcode decode nahi hua.
• ID/EX: reg values, sign-extended immediate, PC+4, dest-#, aur teeno bundles (EX+MEM+WB) carry karta hai.
• EX/MEM: ALU result, store data, branch target, Zero, dest-#, MEM+WB carry karta hai (EX drop ho gaya).
• MEM/WB: memory data, ALU result, dest-#, sirf WB carry karta hai (MEM drop ho gaya).

Degenerate/edge cases jo survival rule automatically handle karta hai:

• add (koi memory access nahi): MemRead=MemWrite=0 EX/MEM ke across ride karte rehte hain — woh present hain lekin inactive. Wall instruction type nahi jaanti; woh bas bits carry karti hai.
• sw (koi write-back nahi): RegWrite=0 WB tak ride karta hai aur simply write disable kar deta hai. Dest-# abhi bhi carry hota hai lekin ignore ho jaata hai.
• beq (branch): branch target aur Zero flag MEM mein hi toh kaam aate hain; non-branch instructions ke liye wahi wires harmless unused values carry karti hain.

PICTURE: staircase — chaar walls, har ek apne control column mein thodi chhoti, bundles apne consuming stage par peelti hui.

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Ek picture ka summary

Neeche: chaaon red walls ke saath poora pipeline, RegWrite signal ek bright red thread ke roop mein ID (born) → ID/EX → EX/MEM → MEM/WB → WB (used) tak traced hai, aur har wall par uski bit width annotated hai. Poora derivation, compressed.

Recall Feynman: poora walkthrough plain words mein

Ek register ek box hai jo har clock tick par apni input ki photo khichta hai aur use stable rakhta hai. Humne apni assembly line ke paanch workers ke beech chaar aise boxes rakhe — chaar, kyunki sirf chaar gaps hain (aakhri worker ke baad kuch nahi, kyunki woh sandwich fridge ko deta hai, jo pehle se yaad rakhta hai). Yeh decide karne ke liye ki ek box mein kya jaata hai, main har wire ke baare mein ek hi sawaal poochhta hun: kya line mein koi aage waala abhi bhi yeh chahta hai? Agar haan, toh yeh cross karta hai; agar nahi, toh drop ho jaata hai. Execute→Memory box ke liye maine chaar data wires abhi bhi chahiye (ALU answer, store data, branch target, zero flag), plus ek 5-bit luggage tag jo write-back ko batata hai kaun se register mein likhna hai, plus do paperwork bundles abhi bhi unread (MEM ka aur WB ka). Execute bundle use ho gaya aur phenk diya gaya. Widths add karo: 32+32+32+1+5+3+2 = 107 bits. Har baad wala stage waisa hi karta hai — apna bundle khao, drop karo, baaki pass karo — isliye har box pehle se thoda narrower hota jaata hai.

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Connections

• Parent: Pipeline registers and control signals
• Single-cycle datapath — Step 2 ki register-free starting picture
• Clocking and edge-triggered flip-flops — woh "tick" jo Step 1 ke box ko kaam karta hai
• Control unit design — jahan Step 5 ke signals paida hote hain
• Forwarding and stalling — kyun dest-# carry karna (Step 4) hazard fixes bhi enable karta hai
• Pipeline hazards — woh collisions jo yeh walls aur staggered signals create karte hain