Visual walkthrough — Classic 5-stage pipeline (IF - ID - EX - MEM - WB)

5.2.3 · D2 · Hardware › Processor Datapath & Pipelining › Classic 5-stage pipeline (IF - ID - EX - MEM - WB)

Hum poore walkthrough mein teen simple symbols use karenge. Inhe pehle naam lete hain, kisi bhi picture se pehle, taaki koi bhi cheez kabhi surprise na kare:

Neeche sab kuch ticks count karna hai aur $T_{clk}$ se multiply karna hai. Bas yahi poora derivation hai.

Step 1 — Ek instruction $k$ jobs ki ek chain hai

KYA. Ek single instruction lo. Yeh ek indivisible blob mein nahi ho sakta — yeh actually chhote jobs ka ek sequence hai jo order mein hone chahiye: usse fetch karo, phir decode karo, phir compute karo, phir memory touch karo, phir answer write back karo.

KYUN. Har job ko pichle job ka output chahiye. Tum ek instruction ko decode nahi kar sakte jo tumne fetch nahi ki; tum woh numbers add nahi kar sakte jo tumne read nahi kiye. Yeh forced order hi hai jo ek line (assembly line) ko natural shape banata hai — dekho Register File read in ID jo ALU Design in EX ko feed karta hai.

PICTURE. Neeche, ek instruction $k=5$ boxes se left-to-right flow karti hai. Har box ek job hai; arrows hain "result aage do."

Step 2 — Non-pipelined machine: koi overlap allowed nahi

KYA. Ab $N$ instructions ek aisi machine par run karo jo unhe overlap karne se mana karti hai: instruction 2 box 1 mein tab tak start nahi ho sakti jab tak instruction 1 box $k$ se poori tarah nahi nikal jaati.

KYUN. Yeh hamaara baseline hai — woh cheez jise pipelining ko beat karna hai. Agar hum nahi jaante ki "slow" kaisa dikhta hai, toh "fast" ka koi matlab nahi.

PICTURE. Har instruction puri line akele occupy karti hai, phir agla shuru hota hai. Bade white gaps notice karo: jab instruction 1 "compute" mein hai, "fetch" box idle baitha hai.

Step 3 — Unhe overlap karo: har tick ek nayi instruction

KYA. Wohi boxes rakho, lekin jis moment instruction 1 box 1 (fetch) chhod deti hai, instruction 2 ko box 1 mein enter karne do. Har tick, sab ek box right shift karte hain, aur ek fresh instruction left se slide karti hai.

KYUN. Step 2 mein woh idle boxes wasted hardware the. Overlapping unhe fill kar deta hai: full speed par saare $k$ boxes ek saath $k$ alag-alag instructions par busy hain. Yeh assembly line hai. Woh chhoti trays jo har instruction ki half-done state ko boxes ke beech hold karti hain woh pipeline registers hain (IF/ID, ID/EX, …).

PICTURE. Yeh classic staircase diagram hai. Ek column (ek tick) padho saare boxes ko busy dekhne ke liye; ek row (ek instruction) padho uski 5-box journey dekhne ke liye.

Step 4 — Ticks count karna: "fill" phir "one-per-tick"

KYA. Count karo ki poora staircase kitne ticks leta hai. Do phases:

1. Fill: pehli instruction ko abhi bhi apne poore $k$ ticks chahiye far right tak pahunchne aur finish karne ke liye. Pehla result tick $k$ par aata hai.
2. Steady state: us pehle result ke baad, ek aur instruction right end se har single tick pop out karti hai. $N-1$ instructions baaki hain finish hone ke liye.

KYUN. Hum literally staircase figure padh rahe hain. Pehla finish delayed hai (pipe ko fill hona hai); uske baad har finish ek tick apart hai kyunki poori line ek saath aage badhti hai.

PICTURE. Wahi staircase, ab annotated: orange bracket $k$ fill ticks mark karta hai, magenta bracket $N-1$ one-per-tick finishes mark karta hai.

Step 5 — Do times divide karo: speedup formula appear hoti hai

KYA. Baseline (Step 2) ko overlapped time (Step 4) se divide karo. Speedup = "kitni baar faster."

KYUN. "Factor of $X$ se faster" ka matlab hai purana-time divided by naya-time. Isse zyada kuch nahi.

PICTURE. Do bars, same instructions: lamba $T_{\text{serial}}$ bar short $T_{\text{pipe}}$ bar ke upar; unki lengths ka ratio speedup hai.

Step 6 — Limit: yeh $k$ par kyun cap hoti hai (large $N$)

KYA. $N$ ko enormous push karo (millions of instructions). Dekho fraction kaise settle hota hai.

KYUN. Real programs billions of instructions run karte hain, isliye large-$N$ behaviour wahi hai jo matter karta hai. Hum upar aur neeche $N$ se divide karte hain dekhne ke liye kya bachta hai.

$\frac{Nk}{k+N-1}=\frac{k}{\frac{k}{N}+1-\frac{1}{N}}\underset{N\to \infty }{\to }\frac{k}{0+1-0}=k$

• $\frac{k}{N}$ aur $\frac{1}{N}$ — "fill cost" $N$ instructions par spread hoti hai; jaise $N$ badhta hai woh $0$ tak shrink ho jaate hain.
• Jo bachta hai — sirf $k$. Pipeline zyada se zyada $k$ times faster ho sakti hai, kyunki best case mein $k$ instructions overlap karte hain.

PICTURE. Speedup versus $N$ ka ek curve: yeh climb karta hai aur dashed line $y=k$ ki taraf flatten ho jaata hai, kabhi cross nahi karta.

Step 7 — Edge & degenerate cases (woh corners jinpar tum trip nahi kar sakte)

Har corner ke liye KYA / KYUN / PICTURE, taaki koi scenario surprise na kare:

Annotated figure mein teeno corners side by side dikhaye gaye hain.

Ek-picture summary

Upar ki sab cheez ek single diagram mein collapse hoti hai: staircase (overlap), do brackets ($k$ fill, $N-1$ steady), do comparison bars, aur ratio jo speedup hai — $N\to \infty$ limit $k$ corner mein pinned hai.

Active recall