Load - store architecture model: Visual walkthrough

5.1.9 · D2 · Hardware › Instruction Set Architecture (ISA) › Load - store architecture model

Parent: Load/store architecture model (5.1.9) Yeh page parent ka central result — ki ek load/store machine, zyada instructions issue karne ke bawajood, kaam utne hi ya kam time mein finish kar sakti hai — ko picture-by-picture derivation ke roop mein rebuild karti hai. Hum assume karte hain ki aap kuch nahi jaante. Har symbol earn karke aata hai, pehle se nahi.

Step 0 — Woh ek word jo hum skip nahi kar sakte: register

Kisi bhi formula se pehle, hume ek object chahiye. Register ek choti si storage box hai CPU ke andar jo ek number hold karti hai. Yeh memory nahi hai — yeh closer hai, faster hai, aur inki ginti bahut kam hoti hai.

Figure — Load - store architecture model

Picture dekho. CPU ek chota sa kamra hai. Registers wo thodi si boxes hain jo desk par rakhi hain. Memory wo badi si shelves ki deewar hai jo saamne wali gali mein hai. Un dono ke beech sirf do darwaze hain jinpar likha hai LOAD (shelves se ek box desk par lana) aur STORE (ek box wapas le jaana). Load/store architecture ka rule lal rang mein draw kiya gaya hai: arithmetic unit ke haath kabhi us gali tak nahi pahunchte. Woh sirf desk ki boxes ko chhoota hai.

Step 1 — Ek "job" kya hota hai: operations ginना

KYA. Hum ek computation ko describe karte hain ki usse kitne real arithmetic/logic steps chahiye. Us number ko kehte hain:

$N_{ops}$

$N_{ops}$ — kitne add / multiply / compare actions algorithm ko sach mein chahiye. Yeh problem ki property hai, machine ki nahi.

KYU. Dono machine styles ko same math karni hai, isliye $N_{ops}$ common ground hai. Difference yeh hai ki data move karne ke liye har style ko kitne extra instructions chahiye.

PICTURE.

Hamara running example hai $c = a + b$ jahan $a$ , $b$ memory mein hain aur $c$ wapas memory mein jaata hai. Math khud ek add hai, toh $N_{ops} = 1$ . Is page par baaki sab kuch darwaazon ke baare mein bookkeeping hai.

Step 2 — Har style ke liye instructions ginना

KYA. Do machine philosophies (dekho RISC vs CISC philosophy):

Register-memory (x86-jaisi): arithmetic instruction ko memory mein jaane ki ijazat hai. Toh ek instruction load-add-store kar sakta hai.
Load/store (RISC-jaisi): arithmetic sirf registers dekhti hai, isliye har memory value ko apna alag darwaaza instruction chahiye.

YEH formula kyun aur koi fancy cheez kyun nahi. Hum sirf darwaazon se guzarte boxes gin rahe hain. $c = a + b$ ke liye: $N_{ops} = 1$ , $N_{loads} = 2$ ( $a$ fetch karo, $b$ fetch karo), $N_{stores} = 1$ ( $c$ likho). Toh:

$I_{rm} = 1, I_{ls} = 1 + 2 + 1 = 4$

PICTURE.

Load/store ka column zyada lamba hai — 4 bricks vs 1. Agar instruction count hi poori kahani hoti, toh hum yahan ruk jaate aur register-memory ko winner declare kar dete. Yeh poori kahani nahi hai, aur agle steps batate hain kyun.

Step 3 — Hidden variable: time per instruction

KYA. Saari instructions cost mein barabar nahi hoti. Hum cost clock cycles mein naapte hain. Clock cycle CPU ke internal metronome ki ek tick hai. Define karo:

$CPI = Cycles Per Instruction (average)$

$CPI$ — average mein, har instruction kitni metronome ticks consume karti hai. Chhota acha hota hai.

YEH ABHI kyun introduce kiya. Step 2 ne instructions gine the lekin pretend kiya ki sab ek jitna time lete hain. Yahi woh galti hai jiske baare mein parent note warn karta hai. Ek register-memory ADD [addr], EAX secretly read-modify-write karta hai; agar memory slow hai, toh woh ek instruction kai ticks tak baitha wait karta rahega.

PICTURE.

Do instructions, brick-count mein same "1", lekin time mein bilkul alag widths. Lal bar ek memory-touching instruction hai jo cache miss par drag kar rahi hai (ek "miss" = value fast nearby cache mein nahi thi, toh hum dur wali shelves ka wait karte hain — dekho Memory hierarchy). Width, count nahi, woh hai jo clock naapti hai.

Step 4 — Overlap: kyun lamba column chhota ho jaata hai

KYA. Ek pipeline har instruction ko stages mein tod deta hai (fetch, decode, execute, memory, write-back) aur ek waqt mein kai instructions par kaam karta hai, jaise assembly line — dekho Instruction pipelining. Toh jab ek slow LOAD memory ka wait kar raha hota hai, ek independent ADD doosre stage mein chal raha hota hai.

YEH YAHAN kyun matter karta hai. Load/store machine ke alag loads aur stores bilkul wahi pieces hain jinhein ek pipeline overlap kar sakti hai. Register-memory machine ka fused instruction apni internal read-modify-write ko overlap nahi kar sakta — woh ek indivisible lump hai.

PICTURE.

Upar wali row (register-memory): ek mota lal lump, ~10 cycles, kuch nahi hai jiske peeche chhupao. Neeche wali row (load/store): do loads aur ek add ek doosre ke upar slide karte hain; doosra miss pehle wale ke neeche thoda tuck ho jaata hai. Jo matter karta hai woh hai total wall-clock width, aur overlap Step 3 ke lamba column ko squeeze karta hai.

Step 5 — Overlap ko ek number mein convert karna: average CPI

KYA. Average CPI hai total pipeline cycles divided by instructions ki ginti:

$CPI_{avg} = \frac{total pipeline cycles}{number of instructions}$

numerator — woh real wall-clock ticks jinmein poora sequence laga (overlap ke baad).
denominator — kitni instructions mein hum us cost ko divide kar rahe hain.

DIVIDE KYUN. Overlap ek slow instruction ki cost uske neighbours ke saath "share" karta hai. Divide karna us sharing ko per-instruction average ke roop mein capture karta hai.

Parent ke textbook numbers use karte hue — overlapped 3-instruction load/store sequence 12 cycles leta hai, un-overlappable single fused instruction 10 leta hai:

$CPI_{ls} = \frac{12}{3} = 4, CPI_{rm} = \frac{10}{1} = 10$

PICTURE.

12 cycles 3 bars mein spread ho jaate hain → har bar sirf 4 ticks lamba hai. 10 cycles 1 bar par baithe hain → 10 ticks lamba. Load/store ka lal average kam hai, precisely isliye kyunki spread karne ke liye zyada bars the.

Step 6 — Master formula: execution time

KYA. Sab kuch ek equation mein combine ho jaata hai real time ke liye:

$T = I \times CPI \times T_{clk}$

$I$ — instruction count (Step 2).
$CPI$ — average cycles per instruction (Step 5).
$T_{clk}$ — seconds per clock tick $= 1/ f_{clk}$ , jahan $f_{clk}$ clock frequency hai. Simpler instructions → shorter critical path → higher $f_{clk}$ → smaller $T_{clk}$ .

TEENO KO KYUN multiply karo. Time = (kitni instructions) × (har ek ke ticks) × (ek tick ke seconds). Units cleanly cancel ho jaati hain: $instr \times \frac{cyc}{instr} \times \frac{s}{cyc} = s$ .

Parent ke numbers plug karo. Load/store faster clock karta hai ( $f = 3 GHz \Rightarrow T_{clk} = 0.33 ns$ ); register-memory slower clock karta hai ( $f = 2.5 GHz \Rightarrow T_{clk} = 0.4 ns$ ):

$T_{rm} = 1 \times 10 \times 0.4 ns = 4.0 ns$ $T_{ls} = 3 \times 4 \times 0.33 ns \approx 4.0 ns$

PICTURE.

Teeno factors ko trade off karte dekho. Load/store $I$ mein haarta hai (4 vs 1... yahan 3 executed steps ke roop mein dikhaya gaya hai), lekin $CPI$ aur $T_{clk}$ dono mein jeetta hai. Do lale products same wall-clock height par utarte hain — aur real chips mein load/store side neeche dip kar jaata hai, better pipelining aur out-of-order execution ki wajah se (dekho Instruction pipelining aur Register allocation).

Step 7 — Degenerate cases (kabhi gap mat chhodho)

Upar ka har claim apne extremes mein survive karna chahiye.

Teen chote panels, ek per case, har ek mein lal winning bar — proof ki conclusion inputs ke poore space mein hold karta hai, sirf us saaf sutre example mein nahi.

Ek-picture summary

Left se right padho: zyada bricks ( $I ↑$ ) chhote bars mein jaate hain ( $CPI ↓$ overlap se) jo faster tick mein jaate hain ( $T_{clk} ↓$ simple decode se), aur teeno multiply hokar ek wall-clock time dete hain jo utna bura nahi — aam tor par better. Lal arrow parent note ki poori thesis hai ek ही stroke mein.

Recall Feynman retelling — plain words mein apne aap se kaho

Socho ek chef hai jo sirf counter par pakaa sakta hai. Ingredients ek fridge mein hain jo kamre ke us paar hai. Har ingredient ko bahar carry karna padta hai (ek load) aur har dish ko wapas carry karna padta hai (ek store); chef ka chaaku kabhi fridge ke andar nahi pahunchta. Ek rival chef ko fridge ke andar seedha kaaтне ki ijazat hai — teen ki jagah ek motion.

Aap andaza lagaoge ki rival faster hai: kam motions! Lekin har fridge-reach rival ko fridge ka door khulne ka wait karvata hai, aur wait karte waqt woh kuch nahi kar sakta. Hamara saaf-suthra chef, meanwhile, agli ingredient us waqt bahar le aata hai jab pichli kaat-paat ho rahi hai — ek assembly line. Uske motions zyada hain lekin har ek short hai, predictable hai, aur overlappable hai, aur kyunki uske moves itne simple hain uske haath overall faster chalte hain.

Total time hai (motions ki ginti) × (ek motion ka time) × (haathon ki speed). Saaf-suthra chef pehla factor haarta hai aur doosre do jeetta hai — aur product barabar ya better nikalta hai. Yahi poora load/store argument hai.

Recall Rapid self-check

Load/store zyada instructions kyun issue karta hai? ::: Arithmetic sirf registers ko chhooti hai, toh har memory value ko apna alag explicit LOAD ya STORE instruction chahiye. Execution time ke teeno factors kya hain? ::: $I$ (instruction count), $CPI$ (cycles per instruction), $T_{clk}$ (seconds per cycle). Zyada instructions ke bawajood load/store ka CPI kam kyun hai? ::: Ek pipeline uske alag loads/stores/ops ko overlap karta hai, toh slow memory access ki cost neighbours mein share ho jaati hai. Load/store ka $T_{clk}$ chhota kyun hai? ::: Simple, uniform instructions ek shorter critical path aur simpler decode deti hain → higher clock frequency. All-cache-hit case mein kaun jeetta hai aur kyun? ::: Load/store, kyunki memory penalty gayab ho jaati hai aur faster clock decide karta hai.

Dekho bhi: Addressing modes · Instruction encoding · RISC vs CISC philosophy · Instruction pipelining