RISC-V base ISA (RV32I - RV64I): Visual walkthrough

5.1.7 · D2 · Hardware › Instruction Set Architecture (ISA) › RISC-V base ISA (RV32I - RV64I)

Step 1 — Ek number sirf boxes ki ek row hai

KYA HAI. Kisi bhi instruction se pehle, aao agree karein ki "bit pattern" ka matlab kya hota hai. 32 chhote boxes ek row mein kheencho. Har box ek bit (binary digit) hai: yeh ya toh 0 rakhta hai ya 1. Hum inhe right se number karte hain, 0 se shuru karke, left par 31 tak.

Right se number kyun karte hain? Kyunki sabse right wala box "ones" box hai — sabse chhoti amount jo aap add kar sakte hain. Uske left ka har box apne pehle wale se double worth ka hota hai: 1, 2, 4, 8, 16, … Position $k$ par box ki value $2^{k}$ hoti hai.

PICTURE. Figure dekho: green box (position 0) ki value $2^{0} = 1$ hai; lavender box (position 3) ki value $2^{3} = 8$ hai. Poori row jo number represent karti hai woh bas har us box ki "worth" ka sum hai jo 1 rakhta hai.

Figure — RISC-V base ISA (RV32I - RV64I)

Step 2 — 32 boxes ko named fields mein kaato

KYA HAI. Ek raw 32-bit row apne aap mein kuch nahi hoti. CPU ise fields mein slice karta hai — boxes ke fixed groups, jinka ek kaam hota hai. Hum R-type layout (register–register, e.g. add) ko apne worked example ke roop mein use karenge.

Yeh exactly yahi cuts kyun? Kyunki designers ne promise kiya tha: rs1, rs2, rd kabhi nahi hilte. Jahan bhi kisi instruction mein source ya destination register hota hai, woh har baar same boxes mein hota hai. Isse decoder register numbers ko turant grab kar sakta hai, chahe use abhi pata bhi na ho ki instruction kya karta hai.

PICTURE. Strip 6 coloured chunks mein split hai. Inhe right-to-left padho kyunki sabse right wala field (opcode) woh pehli cheez hai jo hardware inspect karta hai.

Step 3 — Ek concrete R-type decode karo: `add x5, x6, x7`

KYA HAI. Aao ek real instruction ke boxes fill karte hain: add x5, x6, x7 ( $x 6 + x 7$ ko $x 5$ mein daalo). Hum Step 2 ke fields mein numbers plug karte hain.

Haath se kyun karte hain? Taaki aap dekh sako ki "assembly" aur "32 boxes" ek hi cheez hain, do alag tareekon se likhi gayi. Assembler bas yeh table lookup kar raha hai.

PICTURE. Har field apni value ke saath light up hota hai. Human-readable line se neeche uske boxes tak arrows follow karo.

Toh poora 32-bit word hai 0000000 00111 00110 000 00101 0110011. Yahi hai add x5, x6, x7. Ek form fill karne se zyada mysterious kuch nahi.

Step 4 — Ab interesting wala: ek immediate

KYA HAI. Register ops sirf buckets combine karte hain. Lekin hume constantly constants ki zaroorat hoti hai — "4 add karo", "1 subtract karo". Yeh instruction ke andar hi rehte hain immediate ke roop mein (code mein bake kiya hua number). Hum I-type format ki taraf switch karte hain, jo addi, lw, jalr mein use hota hai.

Naya format kyun? Hume constant ke liye jagah chahiye. I-type rs2 aur funct7 boxes (kul 12 boxes) sacrifice karta hai aur unhe ek single 12-box immediate field ko top [31:20] par de deta hai.

PICTURE. Step 2 se compare karo: top 12 boxes ab ek purple imm block hain. Khaas baat yeh hai ki rs1, funct3, rd, opcode abhi bhi same jagah hain — promise kaayam hai.

Step 5 — Iska dil: sign-extension

KYA HAI. Immediate sirf 12 boxes ka hai, lekin register 32 boxes (XLEN) ka hai. Unhe add karne ke liye pehle hume 12-box number ko 32 boxes tak stretch karna hoga. Rule hai sign-extension: immediate ke top box (uska sign box, position 11) ko uske upar ke sab naye boxes mein copy karo.

Top bit copy kyun karte hain, sirf zeros se pad kyun nahi karte? Two's Complement ki wajah se: us scheme mein top box ka matlab "negative" hota hai. Agar hum zeros se pad karte, toh -1 (barah 1s ke roop mein stored) achanak ek bada positive number ban jaata. Sign box ko copy karna value ko same rakhta hai. Yeh is page ka sabse important idea hai — figure mein dekho.

PICTURE. Do cases side by side:

Top box = 0 (positive): naye boxes 0 se fill hote hain. Value unchanged, e.g. +5 +5 hi rehta hai.
Top box = 1 (negative): naye boxes 1 se fill hote hain. 1111 1111 1111 ( $- 1$ ) 1111…1111 ban jaata hai (abhi bhi $- 1$ ).

Step 6 — `addi x5, x6, -1` execute hote dekho

KYA HAI. Sab kuch combine karo: fields decode karo, immediate sign-extend karo, add karo, store karo. Yeh $x 6 - 1$ produce karta hai jabki poore ISA mein koi subtract-immediate instruction nahi hai.

Ek instruction add aur subtract dono kyun cover karta hai? Kyunki ek negative immediate hi subtraction hai. Sign-extension -1 ko saare 32 boxes mein -1 jaisa behave karata hai, toh x6 + (−1) exactly x6 − 1 hota hai.

PICTURE. Ek chhoti pipeline: boxes → decode fields → sign-extend → adder → result bucket.

Step 7 — Edge case: bikhra hua immediate (B-type branch)

KYA HAI. Branches (beq, bne) ke liye immediate non-adjacent boxes mein split hoti hai — yeh scattered lagti hai. Ab hum kyun dikhate hain, aur decoder ise reassemble kaise karta hai.

Scatter kyun karte hain? Do wajahaat, dono speed ke baare mein hain:

rs1, rs2 fixed rakhna (woh promise) — immediate ke liye bacha hua boxes jo registers use nahi karte, toh woh jahan bhi hain wahan hain.
Bit 0 store nahi hota. Instructions hamesha even addresses par hote hain (≥ 2-byte aligned), toh branch target ka lowest bit hamesha 0 hota hai. Ise store karna ek box waste karta. Ise drop karke aur field ko "2 ke steps" maan kar, ek 12-box field double tak pahunchti hai.

PICTURE. Scattered boxes (mint, coral, butter) instruction mein dikhaye hain, phir arrows har ek ko reassembled offset mein uski sahi jagah kheench lete hain — bit 0 mein ek fixed 0 daala jaata hai.

Step 8 — Edge case: 12 boxes ke liye bahut bada constant

KYA HAI. Hum sirf 12 immediate boxes carry kar sakte hain, toh hum 0xDEADBEEF (32 boxes) ek baar mein load nahi kar sakte. Hum do instructions use karte hain: lui upar ke 20 boxes fill karta hai, addi neeche ke 12 fill karta hai. Lekin addi ki signed nature ek correction force karti hai.

"+1" correction kyun? addi ke low 12 boxes signed hain. Hamara low part 0xEEF apna top box (bit 11) set liye hua hai → yeh negative count hota hai ( $- 273$ ). Jab addi sign-extend karke negative add karta hai, toh yeh upper part se borrow karta hai. Exactly target par pahunchne ke liye hum pre-compensate karte hain: upper part ko 1 se upar round up karo.

PICTURE. Number line: lui hume 0xDEADC000 par utaarta hai; negative addi (−273) hume left chalake 0xDEADBEEF tak le jaata hai. Agar hum 0xDEADB000 use karte, toh leftward walk undershoot karti.

Worked example

x10 mein 0xDEADBEEF load karo

lui   x10, 0xDEADC     # x10 = 0xDEADC000
addi  x10, x10, -273   # 0xEEF as signed = -273

Check karo: $0xDEADC000 + (- 273) = 0xDEADBEEF$ . ✅ li pseudo-instruction yeh "+1 to the top" automatically karta hai.

Ek-picture summary

Upar sab kuch, compressed: 32 boxes → fixed fields mein slice karo → immediate sign-extend hoti hai (bit 11 copy karo) → adder / program counter ko feed karo. Scatter aur "+1" trick sirf do rules ke consequences hain: registers kabhi nahi hilte aur immediates signed hoti hain.

Recall Feynman retelling — ek dost ko batao

Ek RISC-V instruction 32 light-switches ki ek row hai. CPU hamesha same switches dekhta hai kaun se buckets use karne hain — woh switches kabhi nahi hilte, chahe koi bhi instruction ho, toh woh turant buckets padhna shuru kar sakta hai. Jab ek instruction apne andar ek chhota number rakhti hai (ek "immediate"), woh number sirf 12 switches wide hota hai, lekin buckets 32 (ya 64) wide hote hain — toh CPU number ko apna sabse baya switch copy karke upar tak stretch karta hai. Yahi copy trick poora secret hai: yeh negative numbers ko negative rakhti hai, yahi wajah hai ki negative number ke saath add hi subtraction hai, aur isliye koi alag subtract-immediate nahi hoti. Branches ke liye number ke switches idhar-udhar bikhere hote hain (bucket switches fixed rakhne ke liye) aur sabse neeche wala switch chhaod diya jaata hai kyunki instructions hamesha even addresses par hoti hain — ise chhodna jump ki range double kar deta hai. Aur jab ek constant 12 switches ke liye bahut bada ho, toh lui se top load karo, phir addi se bottom add karo — lekin bottom signed hone ki wajah se, borrow cancel karne ke liye top ko 1 se bump up karo. Do rules — buckets stay put, numbers are signed — har ek quirk explain karte hain.

Related: Two's Complement · Addressing Modes · Assembler & Pseudo-instructions · RISC vs CISC · Pipelining · back to RISC-V base ISA (RV32I - RV64I).