Visual walkthrough — Register file organization

5.1.4 · D2 · Hardware › Instruction Set Architecture (ISA) › Register file organization

Shuru karne ke liye sirf teen plain-word ideas chahiye, toh aao unhe ek baar naam dein:

Step 1 — Ek storage cell (the atom)

KYA HAI. Hum sab se chhote possible piece se shuru karte hain: ek single box jo ek bit yaad rakhti hai. Hardware mein yeh box ek D flip-flop hota hai. Iske paas ek data-in wire hoti hai, ek data-out wire hoti hai, aur ek clock tick hoti hai jo use batati hai "ab, data-in par jo bhi hai use capture karo aur pakad lo."

YAHAAN SE KYU shuru karein? Kyunki ek register file kuch nahi hai sirf inhi boxes ka ek bada grid. Agar tum ek box samajhte ho aur yeh (a) andar dekhna aur (b) use badalna, toh tum poori file samajhte ho — baki sab kuch sirf yahi ek saath bahut saare boxes ke liye karna hai.

PICTURE. Figure mein ek cell dikhaya gaya hai. Green arrow data hai jo clock edge par andar aa raha hai; orange arrow woh value hai jo bahar padhi ja rahi hai. Chhota triangle clock input mark karta hai — ise box ki heartbeat samjho.

Step 2 — Cells ko ek register mein stack karo (width $n$)

KYA HAI. Ek box ek bit rakhta hai, lekin hum poore numbers par compute karte hain. Toh hum $n$ boxes side by side rakhte hain aur unhe ek shared clock aur ek shared write-enable line dete hain. Woh bundle ek single register hai: $n$ bits jo saath mein update hote hain.

KYUN. Ek $32$-bit number $32$ bits hai jo ek unit ke roop mein store aur fetch hone chahiye — tum kabhi nahi chahoge ki number ka aadha update ho. Ek enable line share karna guarantee karta hai ki saare $n$ bits ek hi tick par capture karein, ya koi bhi na kare.

PICTURE. Neechey, Step 1 ke $n$ cells ek row mein draw kiye gaye hain. Upar ki single teal wire shared write-enable hai; jab yeh clock tick par $1$ hoti hai, saare $n$ boxes ek saath apna input latch karte hain.

$\underset{\text{one row}}{\underbrace{\text{register}}}=\underset{\begin{array}{c}\text{how many}\\ \text{bits wide}\end{array}}{\underbrace{n}}\times \underset{\text{Step 1 box}}{\underbrace{\text{cell}}}$

Upar har symbol: $n$ = width (ek number mein kitne bits); "cell" = Step 1 ka single box; product ka matlab hai "ek register un $n$ copies hai us box ki jo ek enable se wired hain".

Step 3 — Registers ko file mein stack karo ($N=2^k$ rows)

KYA HAI. Ab $N$ un registers ko vertically stack karo. Woh grid hi register file hai: $N$ rows, har ek $n$ bits wide.

$N=2^k$ number kyun? Kyunki hum har row ko ek $k$-bit address se naam denge, aur ek $k$-bit binary number exactly $2^k$ alag-alag rows ko point kar sakta hai — na zyada, na kam. $N$ ko power of two chunna matlab koi bhi address waste nahi jaata. Agar $k=5$ hai, toh $N=2^5=32$ rows hain, jo exactly common case hai.

PICTURE. Ek grid: rows registers hain (labelled R0, R1, ... R$(N-1)$), columns bit positions hain. Storage boxes ki total number poora grid hai.

$\underset{\begin{array}{c}\text{number of}\\ \text{registers}\end{array}}{\underbrace{N}}=2^{\stackrel{\text{address bits}}{\overbrace{k}}},\underset{\text{total stored bits}}{\underbrace{N\cdot n}}=\underset{\text{rows}}{\underbrace{2^k}}\times \underset{\text{cols}}{\underbrace{n}}$

$N$ = kitni rows; $k$ = address mein kitne bits hain jo row pick karta hai; $N\cdot n$ = grid mein har ek box. $N=32,n=64$ ke liye yeh $32\times 64=2048$ state boxes hain.

Step 4 — Reading: ek wire par EK row pick karo (the MUX)

KYA HAI. Hamare paas $N$ rows hain lekin ALU ek baar mein ek read wire par sirf ek hi dekh sakta hai. Humein ek gadget chahiye jo ek address le aur matching row ka output us wire par select kare. Woh gadget ek multiplexer (MUX) hai: ek many-in, one-out switch jo address se steer hota hai.

MUX kyun aur kuch nahi? Read problem ki shape hi yahi hai ki "diye gaye $N$ candidates aur ek chosen index mein, chosen wala single output wire par daalo." Yeh sentence MUX ki definition hai. Hum MUX ke liye pahunchte hain kyunki problem literally "ek wire par kai mein se ek select karo" hai — koi aur block exactly yeh nahi karta. $k$-bit address se steer hone wala $2^k$-to-$1$ MUX poora kaam karta hai.

PICTURE. Figure mein saare $N$ row-outputs ek bade trapezoid (MUX) mein enter karte dikhaye gaye hain. Ek plum-coloured $k$-bit address narrow side mein enter karta hai aur exactly ek input ko seedha single read port wire par, right side par, steer karta hai. Highlighted path follow karo: sirf addressed row output tak pahuncha hai.

Step 5 — Writing: ek wire ko ONE row mein wapas route karo (the decoder)

KYA HAI. Writing reading ka reverse hai: ek incoming value exactly ek chosen row mein land karni chahiye. Hum destination address lete hain, use ek decoder mein feed karte hain, aur decoder apni $2^k$ output lines mein se ek ko light up karta hai. Hum us line ko ek global WriteEnable ke saath AND karte hain; sirf woh row jis ki line high hai next clock tick par data capture karti hai.

Decoder + enable kyun? Write problem hai "ek wire → kai rows mein se ek", MUX ka mirror. Ek decoder ek $k$-bit address ko $2^k$ lines mein turn karta hai jisme exactly ek line hot hoti hai — precisely "kaunsi row likhni hai" signal. AND-with-WriteEnable safety catch hai: koi bhi row tab tak nahi badalti jab tak hum deliberately na kahein "ab likho."

PICTURE. $k$-bit write address ek decoder mein enter karta hai (left). Iske $N$ output lines mein se, exactly ek (highlighted orange) $1$ hai. Woh line teal WriteEnable ke saath AND hoti hai aur Step 2 ke us ek register ki cells ki shared enable ban jaati hai. Green data bus saari rows tak pahunchti hai, lekin sirf enabled row use latch karti hai.

Step 6 — Ek saath do read ports (MUX replicate karo)

KYA HAI. Ek real instruction add rd, rs1, rs2 ko same cycle mein dono source rows chahiye. Ek MUX humein ek cycle mein ek row deta hai, toh hum ek second independent MUX banaate hain jo same grid of cell-outputs padh raha hai, second address se steer ho raha hai. Ab rs1 aur rs2 saath bahar aate hain.

Replicate kyun, reuse kyun nahi? Ek single MUX apne output par ek cycle mein sirf ek row rakh sakta hai — use reuse karna do reads ko do cycles mein serialise kar deta, single-cycle execution khatam kar deta. Do ports matlab do alag selection paths same stored bits se. Stored boxes shared hain; sirf read machinery duplicate ki gayi hai. Yahi hai jo physically "$R=2$ read ports" ka matlab hai.

PICTURE. Same grid, ab iske upar do trapezoid MUXes lage hain — burnt-orange wala address A se steer hokar read port 1 deta hai, teal wala address B se steer hokar read port 2 deta hai. Dono ek saath identical cell outputs se draw karte hain.

$\underset{\text{read ports}}{\underbrace{R}}=2,\underset{\text{write ports}}{\underbrace{W}}=1⟹\text{two MUXes, one decoder}$

$R$ = independent read MUXes ki number; $W$ = independent write decoders ki number. 2-aur-1 combo exactly 2-operand ALU op ki shape hai.

Step 7 — Ports SQUARE kyun cost karte hain (wiring picture)

KYA HAI. Ab punchline. Har read port har cell par wires bichhaata hai (taaki jo bhi row select ho use reach kar sake), aur har write port bhi yahi karta hai. Toh ek cell par cross hone wale wires $(R+W)$ ke saath badhte hain. Lekin ek port add karna har cell ko fatness bhi deta hai — use zyada word-lines (horizontal) aur zyada bit-lines (vertical) chahiye — toh har cell ki height aur width dono $(R+W)$ ke saath badhte hain. Area = height $\times$ width, toh yeh $(R+W)\times (R+W)$ ke roop mein badhta hai.

YEH KYUN MATTER KARTA HAI. Yeh square law wohi reason hai kyun register files chhoti aur kam-ported rehti hain. Yeh koi scary formula nahi hai — yeh bas "ek cell ki height aur width dono ports ke saath stretch hoti hai" hai.

PICTURE. Ek cell do baar draw ki gayi hai: left mein $R=2,W=1$ ke saath (thin), right mein $R=4,W=2$ ke saath (dono directions mein fat). Horizontal word-lines aur vertical bit-lines count ki gayi hain taaki tum dekh sako height $\propto (R+W)$ aur width $\propto (R+W)$.

Step 8 — Degenerate row: R0 zero se hardwired

KYA HAI. Ek special row ke liye — register $0$ — hum koi bhi flip-flop nahi banaate. Iska read-MUX input simply constant $0$ se tied hai, aur iska decoder write-line disconnected chhooda jaata hai taaki writes gayab ho jaayein.

Yeh edge case kyun? Iska kuch kharcha nahi (low se tied wire free hoti hai) phir bhi har program ko constant $0$ ka permanent source milta hai. Yeh kai instructions ko us ALU mein collapse karta hai jo tumhare paas already hai: mov rd, rs ban jaata hai add rd, rs, r0; nop ban jaata hai add r0, r0, r0. Degenerate row ek feature hai, gap nahi.

PICTURE. R0 row draw ki gayi hai apne boxes grey/removed ke saath; iska MUX line $0$ se pinned hai, iska write-enable line cut hai. Iske saath ek normal row compare karo.

Ek-picture summary

Upar sab kuch, compressed: beech mein cells ka shared grid; do read MUXes (source addresses A, B se steer hoke) ALU ko operands nikaale de rahe hain; ek decoder + WriteEnable ALU result ko destination row mein wapas route kar raha hai; R0 low se tied. Trace green = write path, orange/teal = read paths, plum = address/steering.

Connections

• Register file organization — yeh page us note ke result ki from-zero derivation hai.
• Multiplexers and Decoders — Steps 4 aur 5 exactly yahi do blocks hain.
• Datapath and ALU — Step 9 dikhata hai read ports feed karte hue, aur write port drain karte hue, ALU ko.
• Pipeline Hazards — same-cycle read/write case Step 6 mein hint kiya gaya hai.
• Memory Hierarchy — yeh grid storage ka fastest tier hai.
• RISC vs CISC — R0 tricks (Step 8) ek RISC hallmark hain.
• Yeh note Hinglish mein padho →