Visual walkthrough — Instruction formats and encoding

5.1.2 · D2 · Hardware › Instruction Set Architecture (ISA) › Instruction formats and encoding

Hum assume karte hain ki tum binary mein count kar sakte ho, bas itna kaafi hai. Agar "opcode" ya "register" jaisa koi word fuzzy lag raha hai, toh Instruction Set Architecture (ISA) aur Registers and the Register File notes ground floor hain.

Step 1 — Khaali ruler: 32 slots fill hone ka intezaar kar rahe hain

KYA. Ek CPU jo fixed-length encoding use karta hai, woh har baar instruction fetch karte waqt bilkul utne hi bits leta hai. RISC-V 32 bits leta hai. Toh socho ek ruler jisme 32 slots hain, har slot mein ek 0 ya ek 1 hold hota hai.

YAH se KYUN shuru karein. Yeh decide karne se pehle ki kya kahaan jaayega, hum yeh agree karna chahte hain ki kitna space hai. Fixed width ka matlab hai total budget kabhi nahi badlega — toh jo bhi field hum banayenge woh inhi 32 slots mein se carved out hogi. Kuch bhi spill over nahi ho sakta.

PICTURE. Neeche diya ruler slot 0 se start hota hai, jo bilkul right par hai, aur slot 31 tak jaata hai, jo bilkul left par hai. Woh right-to-left counting matter karti hai: slot 0 "least significant" bit hai, jaise 1s digit kisi normal number ke right mein hota hai.

Step 2 — Pehle opcode reserve karo, aur use right edge par pin karo

KYA. Pehla field jo hum place karte hain woh opcode hai — "kya kaam karna hai" wala field. RISC-V ise 7 bits deta hai, aur yeh positions 0–6 mein rehta hai (sabse rightmost 7 slots).

7 bits KYUN, aur right edge KYUN?

• 7 kyun: hum roughly sau-se-zyada operation classes naam dena chahte hain. $N$ alag-alag cheezein naam dene ke liye tumhe $b=\lceil {\log }_{2}N\rceil$ bits chahiye, kyunki $b$ bits se $2^b$ distinct patterns ban sakte hain. $2^7=128$ patterns ke saath hum $>100$ classes comfortably cover kar lete hain. Six bits ($2^6=64$) bahut kam hai.
• Right edge kyun: decoder ko opcode pehle dhundhna hai, isse pehle ki usse pata chale yeh kaun sa format hai. Agar opcode hamesha same fixed slots mein hota hai, toh decode hardware ek single fixed wire tap ho sakta hai — koi searching nahi. Ise positions 0–6 par pin karna ek promise hai jise har format nibhata hai.

PICTURE. Right par 7 orange slots ab claim ho gaye. 25 slots abhi bhi white hain.

Annotation padhte waqt: brace 7 slots span karta hai; label kehta hai yeh 7 bits kaunsi operation class ka jawab dete hain. Yeh Instruction Decode Stage ka pehla sawaal hai.

Step 3 — R-type ko teen registers chahiye: 5 bits each, exactly 5 kyun

KYA. Ek R-type instruction jaise add x5, x6, x7 teen registers naam leta hai: ek destination rd aur do sources rs1, rs2. RISC-V mein 32 registers hain, isliye har register field ko $\lceil {\log }_{2}32\rceil =5$ bits chahiye. Teen fields ki cost $5\times 3=15$ bits hai.

5 kyun, concretely dikhate hain. 5 bits se $2^5=32$ patterns ban sakte hain — 00000 se 11111 tak — exactly ek per register x0…x31. Char bits sirf 16 names dete, register file ka aadha unreachable hota; six bits har register field par ek slot waste karta (aur hamare paas teen hain — 3 wasted slots jo hum afford nahi kar sakte).

PICTURE. Neeche, ek 5-bit field expand karke uske 32 possible codes dikhaye gaye hain taaki tum dekh sako ki 32 registers zero waste aur zero shortfall ke saath fit ho jaate hain — number $2^5$ exactly 32 par land karta hai.

Term by term: rd = destination register (jahaan answer likha jaata hai); rs1, rs2 = do source registers jo read ho rahe hain. Registers and the Register File dekho yeh numbers actually kya select karte hain.

Step 4 — Teen registers ko fixed opcode ke around place karna

KYA. Hum teen register fields ko ruler mein slot karte hain, opcode ko right par untouched rakhte hue. RISC-V ke chosen positions hain: rd bits 7–11 mein, phir funct3 (Step 5 mein aayega) 12–14 mein, phir rs1 15–19 mein, phir rs2 20–24 mein.

Yah arrangement KYUN (deep reason). Magic constraint yeh hai ki rs1 aur rs2 har us format mein same bit positions occupy karte hain jisme woh hote hain. Register-read critical timing path par hai — CPU registers padhna immediately shuru karna chahta hai, decode fully finish hone se pehle bhi. Agar rs1 hamesha bits 15–19 hai, toh register file feed karne wale wires hard-wired hain aur kabhi re-route nahi hote. Yeh puri format family ka sabse important design decision hai, aur yeh Pipelining mein echo karta hai jahaan early register-read decode ke saath overlap karta hai.

PICTURE. Dekho register fields ruler mein fill ho rahe hain jabki orange opcode right par frozen rehta hai.

Ab tak ka running tally: $7(\text{opcode})+5+5+5(\text{teen regs})=22$ bits use ho gaye, 10 slots bache hain.

Step 5 — Do funct fields: twins ko aakhri 10 slots se alag karna

KYA. add aur sub dono ek hi opcode share karna chahte hain (dono "reg-reg arithmetic" hain), toh hume unhe distinguish karne ke liye extra selector bits chahiye. RISC-V ek 3-bit funct3 (positions 12–14) aur ek 7-bit funct7 (positions 25–31) use karta hai. Yeh aakhri $3+7=10$ bits hain.

Selector ko 3 aur 7 mein kyun split karo, ek 10-bit field ki jagah? Kyunki funct3 ek aise spot par baitha hai jo I-type aur S-type formats mein bhi exist karta hai, jo un formats ko ise sub-selector ki tarah reuse karne deta hai bina kuch move kiye. 7-bit funct7 top slots mein rehta hai jinhein immediate-carrying formats apna number rakhne ke liye use karte hain. Split karne se har format leftover holes repurpose kar sakta hai — wahi trick jo baad mein S-type aur B-type ko apna immediate scattered gaps mein split karne deti hai.

PICTURE. Aakhri 10 slots fill ho gaye: 3 violet low half ke middle-left mein, 7 magenta bilkul left par. Ruler ab completely full hai.

Har brace ek field hai; uske neeche number uski bit-width hai. Left-to-right padho (high position → low position), exactly waise jaise picture mein stack hai.

Step 6 — Ek real instruction se fill karo: add x5, x6, x7

KYA. Ab hum encode karte hain — ek human instruction ko 32 actual bits mein badlte hain. add x5, x6, x7 ke liye: opcode = 0110011, funct3 = 000, funct7 = 0000000, rd = 5, rs1 = 6, rs2 = 7.

Yeh numbers KYUN. Har register number ko 5-bit binary mein convert karo kyunki har register slot 5 wide hai: $5=00101$, $6=00110$, $7=00111$. Opcode/funct values woh fixed constants hain jo RISC-V manual ne "add" ko assign ki hain.

PICTURE. Ruler ka har slot ab apna final 0 ya 1 dikhata hai, field ke hisaab se colour-coded, aur upar human field values likhi hain.

Har brace padhte waqt: rs2 ke neeche bits 7 spell karte hain, rs1 ke neeche 6, rd ke neeche 5 — exactly wahi registers jo humne naam liye, apne permanent homes mein baithe hain.

Step 7 — Degenerate case: agar koi field shrink ya vanish ho jaaye toh?

KYA. Har instruction mein teen registers nahi hote. addi x1, x2, 100 mein sirf do registers hain plus ek number (immediate). Toh I-type format rs2 aur funct7 delete karta hai (woh $5+7=12$ slots hain) aur un slots ko milaakar top positions mein ek 12-bit immediate bana deta hai.

Yeh "degenerate" case apne step ka haqdar KYUN hai. Yeh woh boundary hai jahaan R-type template mein bend aata hai: same opcode position, same rd/funct3/rs1 positions — lekin right-hand structure collapse ho jaata hai. Kaunse fields apni jagah rehte hain aur kaunse absorb ho jaate hain yeh dekhna hi har doosre format (S, B, U, J) ko padhne ki key hai. Invariant survive karta hai: opcode, rd, funct3, rs1 kabhi nahi hilte.

PICTURE. Upar R-type ruler, neeche I-type ruler, aligned — taaki 12 slots jo rs2 + funct7 the woh visibly ek immediate block mein merge hote dikhen, jabki char shared fields column-for-column line up karte hain.

Ek-picture summary

Upar likhi sab kuch, compressed: top par khaali 32-slot ruler; requirements jo ise carve karti hain (opcode → 3 registers → 2 funct selectors) arrows ke roop mein neeche point karte hue; beech mein finished R-type layout widths $7-5-5-3-5-7$ ke saath; aur neeche I-type variant jisme rs2 + funct7 immediate mein merge ho raha hai jabki chaar anchor fields apne columns pakde hue hain.

Active recall