Exercises — Instruction formats and encoding

Lowest 7 bits mein opcode hota hai. Wahan kyun: decoder ko yeh jaanna zaroori hai ki kis tarah ka instruction hai pehle — tab hi use pata chalega ki baaki fields kahan hain. Opcode ko ek fixed spot (har format mein bottom 7 bits) par pin karke, fetch/decode hardware use bina kuch aur parse kiye padh sakta hai. Ise box ke bahar lage label ki tarah samjho.

Teen register fields: rd, rs1, rs2. Har ek 5 bits wide hota hai. 5 kyun: RISC-V mein $32$ registers hain (Registers and the Register File), aur $b=\lceil {\log }_{2}32\rceil =5$. Paanch bits exactly $2^5=32$ patterns dete hain — perfect fit, koi waste nahi.

Fixed-length. Har instruction same width ka hai (32 bits = 4 bytes), isliye opcode kabhi move nahi karta. Isi wajah se decoding sasta aur pipelineable hota hai. Variable-length (jaise x86) CPU ko pehle yeh discover karne par majboor kar deta ki har instruction kahan khatam hoti hai.

$b=\lceil {\log }_{2}200\rceil .$ Neighbours check karo: $2^7=128<200$ (bahut kam), $2^8=256\ge 200$ (fit hota hai). Toh $b=8$ bits, future instructions ke liye $256-200=56$ spare patterns baar rakhte hain. Ceil kyun: ${\log }_{2}200\approx 7.64$; tum bit ka fraction nahi kharid sakte, isliye upar round karo.

Registers ko 5-bit binary mein convert karo (har field 5 wide hai): $rd=8=01000,rs1=9=01001,rs2=10=01010.$ Order funct7 rs2 rs1 funct3 rd opcode mein assemble karo: $\underset{funct7}{\underbrace{0100000}}\underset{rs2}{\underbrace{01010}}\underset{rs1}{\underbrace{01001}}\underset{funct3}{\underbrace{000}}\underset{rd}{\underbrace{01000}}\underset{opcode}{\underbrace{0110011}}$ Ek 32-bit string ke roop mein grouped: 01000000101001001000010000110011. Yeh order kyun: decode opcode ko lowest bits se padhta hai aur baayi taraf kaam karta hai, isliye fields exactly wahin hone chahiye jahan decode unhe expect karta hai.

Ek $b$-bit two's-complement number (Two's Complement and Sign Extension) span karta hai $-2^{b-1}\text{se}{2}^{b-1}-1.$ $b=12$ ke saath: $-2^{11}=-2048$ se $2^{11}-1=+2047$ tak. Ek extra negative kyun: pattern 1000...0 sabse negative value hai aur uska koi positive twin nahi hai, isliye negative side ek aage tak jaati hai.

Woh upper 12 bits 12-bit immediate ban jaate hain. I-type layout: $\underset{12}{\underbrace{imm[11:0]}}\underset{5}{\underbrace{rs1}}\underset{3}{\underbrace{funct3}}\underset{5}{\underbrace{rd}}\underset{7}{\underbrace{opcode}}$ Exactly 12 kyun: freed funct7(7) + rs2(5) = 12 contiguous bits upar baith jaate hain, isliye immediate ek clean block hai — 32 bits tak sign-extend karna aasaan hai. Dhyan do ki rs1, funct3, rd, opcode R-type ke same positions par rehte hain — yeh shared layout hi wajah hai ki register-read wiring har format mein identical hai.

Ek store do registers padhta hai (rs1 = base address, rs2 = store kiya jaane wala data), isliye dono register fields apni usual spots par rehne chahiye. Isse sirf holes bachte hain — puraana rd slot (5 bits) aur puraana funct7 slot (7 bits) — immediate ke liye. $\underset{7}{\underbrace{imm[11:5]}}\underset{5}{\underbrace{rs2}}\underset{5}{\underbrace{rs1}}\underset{3}{\underbrace{funct3}}\underset{5}{\underbrace{imm[4:0]}}\underset{7}{\underbrace{opcode}}$ Split kyun, shrink kyun nahi: hum rs2 nahi hata sakte, isliye 12-bit immediate ko ek 7-bit aur ek 5-bit piece mein kaatke do leftover holes mein thuns diya jaata hai. Hardware benefit: ==rs1 aur rs2 kabhi move nahi karte==, isliye register-read logic R, I, S, aur B formats ke liye ek fixed circuit hai. Sirf immediate-reassembly wiring alag hoti hai.

16-bit opcode ke saath, baaki sab ke liye sirf $32-16=16$ bits bachte hain. Ek single R-type ko sirf teen registers ke liye $5+5+5=15$ bits chahiye, plus function selectors — yeh fit nahi hoga, aur ek I-type ke paas useful immediate ke liye almost koi jagah nahi hogi. Asli lesson: 32-bit word ek fixed budget hai. Opcode ko di gayi har bit operands se churi hoti hai. Real ISAs opcode chhota rakhte hain (7 bits) aur operations ko funct3/funct7 ke saath sideways expand karte hain. Yeh ek core RISC vs CISC design pressure hai.

• Opcode: $\lceil {\log }_{2}500\rceil$. Kyunki $2^8=256<500\le 512=2^9$, opcode = 9 bits.
• Har register: $\lceil {\log }_{2}64\rceil =6$ bits. Teen ke liye = 18 bits.
• Total used: $9+18=27$ bits.
• Word hai 32 → spare = $32-27=5$ bits (funct field, flag, ya future growth ke liye usable). Kyun fit hota hai: humne bits sirf wahin kharch ki jahan requirements ne demand kiya aur running sum ko 32-bit budget ke against check kiya — exactly parent ka "total width = sum of field widths" rule.

Fixed costs: opcode $9$ + rd $6$ + rs1 $6=21$ bits. Immediate ko baaki milta hai: $32-21=11$ bits. Two's-complement value (Two's Complement and Sign Extension) ke roop mein, 11 bits span karte hain $-2^{10}\text{se}{2}^{10}-1=-1024\text{se}+1023.$ Signed kyun: "add $-8$" jaisi instructions kaam karni chahiye, isliye top bit sign bit hai aur decode ALU ke touch karne se pehle 11 bits ko 32 tak sign-extend karta hai.

R-type map funct7 rs2 rs1 funct3 rd opcode use karke word slice karo:

• funct7 = 0000000, funct3 = 000 → operation hai add.
• rs2 = 00111 = 7 → source 2 hai x7.
• rs1 = 00101 = 5 → source 1 hai x5.
• rd = 00001 = 1 → destination hai x1. Assembly: add x1, x5, x7 (RISC-V rd, rs1, rs2 likhta hai). Text mein yeh order kyun: assembler destination pehle print karta hai, phir sources — bit layout ka ulta visual order, jo ek classic trip-up hai.

12-bit field ka top bit 1 hai, isliye yeh ek negative two's-complement number hai. Ise padhne ke liye, invert karo aur ek add karo: $111111111000\stackrel{\text{invert}}{\to }000000000111=7\stackrel{+1}{\to }8.$ Toh value hai $-8$. Decode ise sign-extend karta hai (top 1 ko baayi taraf copy karta hai) 32-bit $-8$ tak taaki ALU ek true $-8$ add kare, koi bada positive number nahi. Instruction hai addi rd, rs1, -8.

Do pieces ko sahi order mein concatenate karo — high bits pehle, low bits baad mein: $imm[11:5]\Vert imm[4:0]=0000010\Vert 00100=000001000100.$ Binary mein padho: $000001000100_2$. Set bits positions 6 aur 2 par hain (0 se count karke), toh value $=2^6+2^2=64+4=68$. Top bit 0 hai → positive, sign-extension value nahi badlata. Reassemble kyun: store ka effective address hai rs1 + 68; split purely ek storage trick hai rs1/rs2 ko fixed rakhne ke liye — L3.2 mein S-type map dekho.

Opcode fixed hota hai aur pehle padha jaata hai; baaki fields $\lceil {\log }_{2}N\rceil$ se size hote hain aur word width tak sum hone chahiye; immediates signed, sign-extended, scaled, ya split ho sakti hain — raw bits hamesha value nahi hoti.