Packaging and wire bonding - flip-chip: Visual walkthrough

4.3.22 · D2 · Hardware › Semiconductor Fabrication › Packaging and wire bonding - flip-chip

YE PAGE KYA KARTA HAI. Parent note ne tumhe do headline formulas diye the: $N_{wire} = \frac{4 L}{p} N_{flip} = (\frac{L}{p})^{2}$ Ye page dono ko bilkul scratch se build karta hai — koi formula assumed nahi, har letter earn kiya gaya hai — aur pictures mein dikhata hai kyun ek seedhi line mein barhta hai aur doosra explode karta hai. Akhir tak tum dekh paoge kyun poori industry ne apne chips ulte kar diye. Saath mein hum rounding ke baare mein honest hain — real pad counts whole numbers hote hain, aur hum exactly batate hain jab clean formula galat hota hai, kyun, aur valid (non-negative, integer) answer kaise force karein.

Step 0 — Teen symbols jo hum use kar sakte hain

Kisi bhi formula se pehle, chalo agree kar lete hain har letter ka kya matlab hai, ek picture se anchor karke.

Figure — Packaging and wire bonding - flip-chip

Figure s01 — kya dekhna hai: lavender square die hai (side $L$ , dono red arrows). Top edge ke saath, mint dots pads hain; do dot centres ke beech chhota slate arrow ek pitch $p$ hai. Beech ka khaali hissa $N$ label karta hai, woh count jo hum dhundh rahe hain.

Is poore page ka sawaal:

Agar dono methods same pitch $p$ same die of side $L$ par use karein, toh har ek kitne connections deta hai — aur jaise die barhti hai, woh number kaise barhta hai?

Step 1 — EK edge ke saath count karna (argument ka atom)

KYA. Die ki ek seedhi edge lo, length $L$ ki. Connection points $p$ distance par rakh do, stop-when-full (hamara fixed convention). Kitne fit hote hain?

KYUN. Wire bonding sirf wahi pads tak pahunch sakta hai jo die ke rim par baithe hain (wire bahar se sili jaati hai), isliye edge count karne ki natural unit hai. Ek edge master karo aur baaki sab bookkeeping hai.

PICTURE. Top edge par march karte red dots dekho, aur right end par leftover grey stub notice karo jahan ek poora pitch aur fit nahi hota.

Figure s02 — kya dekhna hai: slate line length $L$ ki die ki ek edge hai (lavender arrow). Coral dots pads hain jo ek pitch $p$ se spaced hain (pehle do ke beech mint arrow). Right par dashed grey stub leftover space hai — $p$ se chhota, toh koi extra pad fit nahi hota. Woh stub exactly wajah hai kyun real count rounded down hoti hai.

Step 2 — Wire bonding saari 4 edges use karta hai (perimeter formula)

KYA. Ek square ke chaar edges hote hain. Wire bonding har ek par pads rakh sakta hai, har edge stop-when-full count ki jaaye. Inhe add karo — lekin chaar corners share hote hain, toh overlap subtract karo.

KYUN. Die face-up hai aur chipka hua hai; wires bahar se aati hain aur sirf border pakad sakti hain. Toh total wire-bond budget border ke sum se aata hai — perimeter — minus corners jo warna double count hoti.

PICTURE. Chaar edges, har ek apni $⌊ L / p ⌋$ dots ki row carry kar raha hai. Die ka middle khaali hai — koi wire wahan nahi pahunchti. Chaar corner dots (circled) dono edges se belong karte hain.

Figure s03 — kya dekhna hai: butter square die hai; coral dots saari chaar edges par hain. Chaar circled dots corners par hain jinhe do edges count karti hain — yahi double-count hai. Center text us wasted interior real estate ko mark karta hai jo flip-chip reclaim karega.

Formula Perimeter (wire-bond) count — integer form, phir scaling form

Exact integer form (woh jo tum actually chip build karne ke liye use karte ho): $N_{wire} = max (4 ⌊ \frac{L}{p} ⌋ - 4, 0)$

$⌊ L / p ⌋$ — ek edge par pads, stop-when-full (Step 1 se).
$\times 4$ — equal length $L$ ki chaar edges.
$- 4$ — chaar corner pads dono edges se share hote hain, toh saari chaar edges sum karne par har corner do baar count hota hai; hum chaar duplicates ek baar subtract karte hain.
$max (\cdot, 0)$ — clamp to zero. Agar die itni chhoti hai ki har edge ek ya kam pad hold kare, $4 ⌊ L / p ⌋ - 4$ negative ho sakta hai, jo bakwaas hai — tum $- 4$ connections nahi rakh sakte. Clamp physically-real answer $0$ force karta hai. (Step 6 exactly batata hai yeh kab kaam aata hai.)

Clean scaling form (sirf growth argument ke liye use hoti hai, kabhi real count ke liye nahi): $N_{wire} \approx \frac{4 L}{p}$ Ye ek saath do approximations drop karta hai, aur yahan precisely kyun har ek allowed hai jab $L ≫ p$ :

har edge par floor drop karna $< 1$ pad per edge kho deta hai ⇒ total $< 4$ pads;
$- 4$ drop karna chaar corners kho deta hai. Dono $O (1)$ constants hain; leading term $4 L / p$ bina bound ke barhta hai, toh unka relative weight $\to 0$ . Chhoti die ke liye ye vanish nahi karte — next box dekho.

Formula Exactly kab

$- 4$ (aur floor) matter karta hai — annotated Leading term ke against corner correction ka relative size: $\frac{correction}{leading term} = \frac{4}{4 L / p} = \frac{p}{L}$

Numerator $4$ — chaar dropped corners.
Denominator $4 L / p$ — clean scaling count.
Result $p / L$ — answer ka woh fraction jo tum phenko clean form use karke. Bada jab $L$ close to $p$ ho (chhoti die), tiny jab $L ≫ p$ .

Die size	scaling $4 L / p$	floored $4 ⌊ L / p ⌋$	integer $max (4 ⌊ L / p ⌋ - 4, 0)$	error $= p / L$
$L = p$	$4$	$4$	$max (0, 0) = 0$	$100%$
$L = 2 p$	$8$	$8$	$4$	$50%$
$L = 10 p$	$40$	$40$	$36$	$10%$
$L = 100 p$	$400$	$400$	$396$	$1%$
$L = 1000 p$	$4000$	$4000$	$3996$	$0.1%$
$L = p$ row dhyan se padho: naive $4 L / p$ kehta hai $4$ , lekin honest integer form clamp karke 0 deta hai — $100%$ error. Real chip ( $L ≫ p$ ) ke liye columns milke aa jaate hain aur correction ek rounding whisper hai.

Step 3 — Flip-chip poora FACE cover karta hai (edges nahi, area fill karta hai)

KYA. Ab die ko ulta karo taaki uska active face neechay point kare, aur poore face par solder bumps ugao, sirf rim par nahi — puri square ko dhakne waali dots ki ek full grid.

KYUN. Jab tum wire se sidha sideways jaane ki bajaye bump se seedha neechay connect karte ho, die ka interior reachable ho jaata hai. Achanak Step 2 ka khaali middle usable real estate ban jaata hai.

PICTURE. Wahi square, ab edge-to-edge bumps se grid mein bhara hua.

Figure s04 — kya dekhna hai: mint square die face-down hai. Lavender dots ise corner-to-corner fill karte hain — woh interior jo s03 mein blank tha ab bumps se bhara hai. Woh reclaimed middle hi poora reason hai ki count ab square hone wala hai.

Step 4 — 2-D grid count karna (rows × columns)

KYA. Grid mein bumps count karo. Har row bas ek edge hai — ye $⌊ L / p ⌋$ bumps hold karta hai (Step 1 phir se, stop-when-full). Phir pucho: upar se neechay stack mein kitni rows hain?

KYUN. Ek grid wahi edge-count hai jo neechay repeat hoti hai. Die ki height bhi $L$ hai (ye square hai), aur rows same pitch $p$ se spaced hain — toh rows ki sankhya bhi $⌊ L / p ⌋$ hai.

PICTURE. Ek row (across) aur ek column (down) highlight karo; dono $⌊ L / p ⌋$ dots hold karte hain.

Figure s05 — kya dekhna hai: top coral row aur left mint column dono mein $⌊ L / p ⌋$ dots hain. Lavender dots grid ka baaki hissa hain. Row count × column count = total bumps — woh multiplication wahan hai jahan power-of-2 paida hoti hai.

Formula Area-array (flip-chip) count — integer form, phir scaling form

Exact integer form: $N_{flip} = bumps per row ⌊ \frac{L}{p} ⌋ \times number of rows ⌊ \frac{L}{p} ⌋ = ⌊ \frac{L}{p} ⌋^{2}$

Pehla floor term — ek row mein kitne bumps across (horizontal), stop-when-full.
Doosra floor term — height $L$ mein vertically kitni rows fit hoti hain.
Rows × columns multiply karna kisi bhi grid ko count karne ka tarika hai — jaise chessboard ko $8 \times 8$ count karna. Koi clamp nahi chahiye: do non-negative floors ka product already $\geq 0$ hai.

Clean scaling form: $N_{flip} \approx (\frac{L}{p})^{2}$

Exponent 2 directly do directions se aata hai: connections ek 2-dimensional resource par rehte hain.
Yahan do floors drop karne se zyada se zyada roughly ek row aur ek column kho sakti hai — ek $O (L / p)$ edge strip, poora $O ((L / p)^{2})$ area nahi. Toh relative error phir $\to 0$ as $L ≫ p$ ; bade grids ke liye floored aur scaling values almost identical hain.

Step 5 — Dono formulas ki race: flip-chip kahan jeet ta hai?

KYA. Dono counts ko die size $L$ (same pitch $p$ ) ke against ek graph par rakho aur crossover dhundho — woh die size jahan flip-chip wire bonding se aage nikal jaata hai.

KYUN. Do formulas tab tak kuch nahi kehte jab tak compare na karo. Crossover batata hai kin chips ke liye bumping ki extra complexity sahi hai.

PICTURE. Ek seedhi line ( $N_{wire}$ ) aur upar ki taraf moodi curve ( $N_{flip}$ ). Woh ek baar milte hain; us point ke baad curve rocket ki tarah aage nikal jaati hai.

Figure s06 — kya dekhna hai: coral seedhi line $4 L / p$ hai; lavender curve $(L / p)^{2}$ hai. Woh slate dot par milte hain ( $L = 4 p$ , dono $= 16$ ). Right par mint shaded wedge woh region hai jahan flip-chip ki curve aage nikal gayi hai — aur woh sirf chauda hota jaata hai.

Formula Crossover solve karna (scaling form)

Clean scaling values use karke ( $\pm$ corrections drop karo, valid kyunki hum sirf crossover ki shape chahte hain), set flip-chip $>$ wire bond: $(\frac{L}{p})^{2} > \frac{4 L}{p}$ $x = \frac{L}{p}$ let karo ("pitch-units mein die") clean karne ke liye: $x^{2} > 4 x ⟹ x > 4 ⟹ \frac{L}{p} > 4 ⟹ L > 4 p$

Humne dono sides $x$ se divide kiya (allowed: $x > 0$ , die ki hamesha positive width hoti hai).
Matlab: jaise hi die 4 pitches se zyada wide ho, area perimeter ko beat karta hai. Real chips hundreds of pitches wide hote hain — toh flip-chip essentially hamesha I/O par jeetta hai.
Caveat, pehle hi bata diya: ye scaling forms use karta hai. $x = 4$ ke paas Steps 2 aur 4 ke integer/clamp corrections exact tie ko ek pad ya do aage-peeche shift kar sakte hain — Step 6 boundary par honest integer values check karta hai.

Step 6 — Degenerate cases (koi scenario andikhaa mat chhodo)

KYA. Formulas ko unki extremes par check karo, taaki baad mein kuch surprise na kare — sub-pitch die sameit jahan fractions whole numbers ban'ne chahiye aur clamp fire karna chahiye.

KYUN. Woh formula jis par tum trust karte ho uske edge cases survive karne chahiye: sub-pitch die, zero-size die, one-pad-per-edge die, aur tie point. Har jagah floor aur $max (\cdot, 0)$ clamp apni jagah earn karte hain.

PICTURE. Chaar mini-panels: ek pitch se chhota die, ek vanishing die, ek single-pad die, aur exact crossover.

Figure s07 — kya dekhna hai: panel 1 ek die dikhata hai ek pitch se chhoda — ek bhi pad fit nahi hota, toh dono counts zero hain. Panel 2 die ko kuch nahi tak shrink karta hai. Panel 3 ( $L = p$ ) mein 4 coral corner-dots (wire) ek akele lavender centre bump (flip) ko beat karte hain. Panel 4 ( $L = 4 p$ ) exact tie dikhata hai, 16 = 16.

Formula Edge-case table — har case walk kiya gaya, floor aur clamp explicit banakar

$0 < L < p$ (die ek pitch se chhodi): $L / p < 1$ , toh $⌊ L / p ⌋ = 0$ . Phir wire $= max (4 \cdot 0 - 4, 0) = max (- 4, 0) = 0$ — yahan exactly clamp fire karta hai: raw $4 ⌊ L / p ⌋ - 4 = - 4$ impossible hai, aur $max (\cdot, 0)$ ise rescue karke $0$ karta hai. Flip $= ⌊ 0 ⌋^{2} = 0$ . Toh dono methods 0 dete hain — die simply itni chhoti hai ki ek bhi pad bond nahi ho sakta. Clean forms yahan $4 L / p$ aur $(L / p)^{2}$ return karti, dono non-zero fractions, yahi exactly wajah hai kyun floor aur clamp mandatory hain.
$L \to 0$ (die kuch nahi tak shrinks): $⌊ L / p ⌋ \to 0$ , toh wire $\to max (- 4, 0) = 0$ aur flip $\to 0$ . Koi die nahi, koi connections nahi. ✅
$L = p$ (die exactly ek pitch wide): $⌊ L / p ⌋ = 1$ . Wire (stop-when-full) $= max (4 \cdot 1 - 4, 0) = max (0, 0) = 0$ plain formula se — kyunki ek pad per edge ke saath, saare chaar pads corners par baithe hain aur corner subtraction unhe hata deti hai. Practice mein ek designer un 4 distinct corner pads rakhega aur 4 count karega; hamara stop-when-full-plus-corner-subtraction formula is tiny regime mein lower bound hai. Kisi bhi tarah, wire ke 4 corner slots flip ke single centre bump ( $⌊ 1 ⌋^{2} = 1$ ) se jeette hain: wire bonding small-die regime mein jeetta hai. Yahi wajah hai kyun tiny chips abhi bhi wire bonding use karti hain.
$L = 4 p$ (the tie): $⌊ L / p ⌋ = 4$ . Wire $= max (4 \cdot 4 - 4, 0) = 12$ (integer form with corner fix); flip $= ⌊ 4 ⌋^{2} = 16$ . Scaling forms dono $16$ deti hain (Step 5 ka clean crossover); honest integer forms dikhate hain flip tie point tak already aage hai jab corners subtract kiye — corner penalty true crossover ko thoda below $4 p$ nudge karta hai.
$L ≫ p$ (real chips): $L^{2}$ curve $L^{1}$ line ko daba deta hai; floor, $- 4$ , aur clamp sab negligible ho jaate hain ( $O (1)$ growing $O ((L / p)^{2})$ ke against). Flip-chip dominate karta hai.

Ek-picture summary

Figure s08 — kya dekhna hai: left = perimeter method, sirf border par coral dots, count $4 ⌊ L / p ⌋ - 4$ , ek seedhi line; khaala beech kharaab hota hai. right = area array, lavender dots poore face ko bharte hue, count $⌊ L / p ⌋^{2}$ , ek exploding curve. Right par reclaimed middle precisely left ki khaali jagah hai — yahi wajah hai count square hota hai sirf double hone ki bajaye.

Left: perimeter — sirf border par dots, integer count $max (4 ⌊ L / p ⌋ - 4, 0)$ , $4 L / p$ ki tarah scale karta hai, ek seedhi line. Right: area array — pura face fill karte dots, integer count $⌊ L / p ⌋^{2}$ , $(L / p)^{2}$ ki tarah scale karta hai, ek exploding curve. Left par akela khaali beech exactly woh real estate hai jo right-hand picture reclaim karta hai — aur woh reclaimed area hi wajah hai ki count double hone ki bajaye square hota hai.

Recall Feynman retelling — poora walkthrough ek 12-saal ke bacche ko explain karo

Ek square garden imagine karo aur tum flowers plant karna chahte ho. Pitch $p$ woh doori hai jitni flowers ke beech honi chahiye; garden ki side $L$ hai. Toh ek fence ke saath tum lagbhag $L / p$ flowers fit kar sakte ho — rounded down, kyunki tum aadha flower nahi laga sakte, aur agar fence ka aakhri stub bahut chhota hai, woh khaali rehta hai. (Hum hamesha woh rule use karte hain "ek end se shuru karo, jab agla fit na ho ruko.") Purana tarika (wire bonding): tumhe sirf chaar fences ke saath plants karne diya jaata hai. Chaar fences × $⌊ L / p ⌋$ flowers, minus 4 corner flowers jo warna double count ho jaate = $4 ⌊ L / p ⌋ - 4$ . Aur agar ye kabhi negative aaye (ek spacing se chhota garden), use zero par clamp karo — tune simply kuch plant nahi kiya. Poora beech khaali grass rehta hai. Garden twice as big karo aur roughly twice as many flowers milte hain — ek seedhi line. Naya tarika (flip-chip): ab tum poora garden neat rows mein plant karte ho. Har row mein $⌊ L / p ⌋$ flowers hain, aur $⌊ L / p ⌋$ rows hain, toh $⌊ L / p ⌋ \times ⌊ L / p ⌋ = ⌊ L / p ⌋^{2}$ flowers. Garden twice as big karo aur chaar guna zyada milte hain — ye tezi se upar curve karta hai. Agar garden ek flower-spacing se chhota hai, koi bhi flowers fit nahi hote — dono taraf zero. Woh roughly tie karte hain jab garden lagbhag 4 flowers wide ho; koi bhi bada aur poora area fill karna fence-only method ko kuchal deta hai. Woh "area fill karo, sirf edge line mat karo" trick hi poori wajah hai ki chips ko ulta kar diya gaya.

Recall Quick self-test

Ek edge kitne pads hold karta hai (hamara stop-when-full convention)? ::: $⌊ L / p ⌋$ Wire-bond total, exact integer form? ::: $max (4 ⌊ L / p ⌋ - 4, 0)$ $max (\cdot, 0)$ clamp kyun? ::: taaki ek tiny die nonsense negative count na de. $- 4$ correction kab 50% hai? ::: jab $L = 2 p$ (tiny die). Flip-chip total aur kyun squared? ::: $⌊ L / p ⌋^{2}$ ; rows × columns = 2-D grid. $0 < L < p$ ke liye kya hota hai? ::: floor 0 hai, clamp fires — dono methods 0 dete hain. Scaling crossover die size? ::: $L \approx 4 p$ (corners subtract hone par thoda below). Chhoti die like $L = p$ ke liye kaun jeetta hai? ::: Wire bonding (4 corner pads vs 1 bump).

Ye bhi dekho

Ball Grid Array (BGA) — doosra-level area array jo flip-chip ki logic ko board tak le jaata hai.
Signal Integrity and Parasitic Inductance — kyun short bumps electrically long wires ko beat karte hain.
Thermal Management and Heat Sinks — flipped die ki back-side ek cooling surface ban jaati hai.
Coefficient of Thermal Expansion (CTE) Mismatch & Intermetallic Compounds and Bond Reliability — un saare tiny joints ki reliability ki price.
Wafer Dicing — die $L$ pehli jagah kahan se aaya.