Multi-level cell (MLC - TLC - QLC) flash: Worked examples

This deep dive is the calculator companion to Multi-level cell (MLC - TLC - QLC) flash. The parent note built the ideas; here we grind through every kind of number the topic can throw at you, so no exam or real-world case surprises you.

Before we compute anything, let us fix the four tools we reuse. Each is stated in plain words first, then as a formula.

The scenario matrix

Every problem this topic asks lands in one of these cells. The worked examples below are tagged with the cell(s) they cover, and together they hit all of them. We assume $b \geq 1$ throughout; the truly degenerate $b = 0$ (one level, no gaps, stores nothing) is listed as a conceptual boundary only.

#	Case class	What makes it tricky	Example that covers it
C0	Degenerate: $b = 0$ (conceptual edge)	$L = 1$ , $L - 1 = 0$ → $δ V$ undefined; why $b \geq 1$	noted in Ex 3
C1	Given $b$ → find $L$ , $δ V$	plain forward calc, fencepost trap	Ex 1
C2	Given $δ V$ → find $b$ (inverse)	invert $2^{b} - 1$ , round the right way	Ex 2
C3	Degenerate: $b = 1$ (SLC)	$L - 1 = 1$ , single gap — sanity anchor	Ex 3
C4	Limiting: $b$ large (PLC, $b = 5$ )	margin collapse, exponential feel	Ex 4
C5	Ratio / relative crowding	window cancels — pure $\frac{2 ^{b_{1}} - 1}{2 ^{b_{2}} - 1}$	Ex 5
C6	Capacity at fixed die (word problem)	linear in $b$ , unit bookkeeping (bits→bytes)	Ex 6
C7	Gray-code assignment / bit-flip damage	adjacency, verify one-bit rule	Ex 7
C8	Read-reference count + endurance	$L - 1$ comparisons; P/E order-of-magnitude	Ex 8
C9	Exam twist: SLC-cache effective write	mixed-mode, "which number dominates?"	Ex 9
C10	Zero / boundary: overlap threshold	when does $δ V$ hit a smear width?	Ex 10

Worked examples

Worked example 2 — Inverse: how many bits fit a margin? (cell C2)

A manufacturer insists every level needs at least $δ V = 0.5 V$ to stay reliable, with window $Δ V_{w in d o w} = 4.2 V$ . What is the maximum $b$ ?

Forecast: more bits = smaller margin, so a floor on margin puts a ceiling on bits. Guess: 2, 3, or 4?

Start from $δ V = \frac{Δ V _{w in d o w}}{2 ^{b} - 1}$ and demand $δ V \geq 0.5$ . Why? the reliability rule is a lower bound on spacing.
Rearrange: $2^{b} - 1 \leq \frac{Δ V _{w in d o w}}{δ V} = \frac{4.2}{0.5} = 8.4$ . Why? isolate the level count; larger $2^{b} - 1$ means smaller spacing, so it must stay under the ratio.
So $2^{b} \leq 9.4 \Rightarrow b \leq lo g_{2} 9.4 \approx 3.23$ . Why $lo g_{2}$ ? it is the inverse of $2^{b}$ — it asks "which exponent gives this number of levels?"
$b$ is a whole number of bits, so round down: $b = 3$ (TLC). Why down? $b = 4$ would violate the margin; you cannot store a fractional bit per cell.

Verify: at $b = 3$ , $δ V = 4.2/ (2^{3} - 1) = 4.2/7 = 0.6 V \geq 0.5$ ✓. At $b = 4$ , $δ V = 0.28 V < 0.5$ ✗. So 3 is indeed the max.

Worked example 4 — Limiting behaviour: PLC (

$b = 5$ ) (cell C4) Push to Penta-level: $b = 5$ , same $4.2 V$ window. Find $δ V$ and compare to SLC.

Forecast: SLC had $4.2 V$ . Guess PLC's spacing — closer to $0.5$ or $0.1 V$ ?

$L = 2^{5} = 32$ . Why? each added bit doubles levels: 16 → 32.
Gaps $= 31$ . Why? fencepost.
$δ V = \frac{4.2}{31} \approx 0.135 V$ . Why? window split 31 ways.

Verify: ratio to SLC $= \frac{δ V _{P L C}}{δ V _{S L C}} = \frac{1/31}{1/1} = \frac{1}{31} \approx 0.032$ — about 31× tighter. The step from QLC (1/15) to PLC (1/31) more than doubles the crowding, confirming the exponential ( $2^{b} - 1$ ) collapse, not a linear one.

The bar chart below makes this collapse visible: read left to right (SLC→PLC), and notice how the bars do not shrink by a fixed step — each drop is a smaller fraction of the last, because the denominator $2^{b} - 1$ (labelled on each bar as $1/1, 1/3, 1/7, 1/15, 1/31$ ) grows exponentially. The dashed red line is the overlap threshold of Ex 10; the QLC and PLC bars are the ones that dip beneath it.

Figure — Multi-level cell (MLC - TLC - QLC) flash

Worked example 7 — Gray-code damage check (cell C7)

A TLC cell is programmed to level 3 with Gray pattern from the parent's chain (… 011 → 010 …, levels numbered 0..7). Charge leaks and it is misread as the adjacent level 4 (110). How many bits flip? What if it were misread by two levels to level 5 (111)?

Forecast: Gray code promises adjacent = 1-bit difference. Predict the two answers.

Level 3 pattern (0-indexed in the chain 000,001,011,010,110,111,101,100) is 010; level 4 is 110. Why read from the chain? the parent fixed this exact Gray assignment.
Compare 010 vs 110: differ only in the leftmost bit → 1 bit flips. Why does this matter? Error Correction Codes (LDPC/BCH) fixes fewest-flip errors most cheaply, so 1 flip is the best case.
Two-level jump: 010 (lvl 3) vs 111 (lvl 5). Compare digit by digit: $0 \neq = 1$ , $1 = 1$ , $0 \neq = 1$ → 2 bits flip. Why compute this? to show Gray only guarantees the one-level case; bigger jumps cost more.

Verify: the number of differing bits is the Hamming distance. 010⊕110 = 100 (one 1) ✓; 010⊕111 = 101 (two 1s) ✓. Adjacent misreads are the common case (touching smears), so Gray code keeps typical damage at exactly one bit — see Gray Code.

Worked example 9 — Exam twist: SLC-cache effective write (cell C9)

A QLC drive writes an SLC cache at $t_{S L C} = 0.2 ms/page$ , but native QLC pages take $t_{Q L C} = 2.0 ms/page$ . A burst of $100$ pages fits entirely in the cache. Later the drive migrates them to QLC in the background. (a) What write time does the user see per page? (b) What is the true QLC-mode time, and why does the user not feel it?

Forecast: which number governs the felt speed — the small one or the big one?

Burst fits the cache, so all $100$ pages are written in SLC mode: user time $= t_{S L C} = 0.2 ms/page$ . Why? the fast path is what the user waits on; migration happens later, idle.
True QLC time $= t_{Q L C} = 2.0 ms/page$ . Why compute it? to show the background cost.
Speed-up felt by user $= \frac{t _{Q L C}}{t _{S L C}} = \frac{2.0}{0.2} = 10 \times$ . Why the ratio? it quantifies how much the cache hides.

Verify: $0.2 ms \times 100 = 20 ms$ burst felt, vs $2.0 ms \times 100 = 200 ms$ raw — the cache hides $180 ms$ (10×). Caveat (the exam twist): if the burst overflowed the cache, the excess pages would fall back to $2.0 ms$ and the felt speed would collapse — see SLC Cache and SSD Write Amplification.

Worked example 10 — Boundary: when do smears overlap? (cell C10)

Each level's charge distribution has a half-width (from centre to where a read starts misclassifying) of $w = 0.15 V$ . Two neighbours overlap when their half-widths meet, i.e. when $δ V < 2 w$ . For $Δ V_{w in d o w} = 4.2 V$ , at which $b$ does overlap first occur?

Forecast: SLC ( $4.2 V$ ) is safe; guess whether TLC ( $0.6 V$ ) or QLC ( $0.28 V$ ) is the first to fail against $2 w = 0.3 V$ .

Overlap threshold: $2 w = 2 (0.15) = 0.30 V$ . Why $2 w$ ? each of the two neighbours contributes one half-width $w$ toward the gap; they touch when the sum equals $δ V$ .
Compute $δ V$ per $b$ : MLC $= 1.4$ , TLC $= 0.6$ , QLC $= 0.28 V$ . Why list them? to find the first that drops below $0.30$ .
Compare: $1.4 > 0.30$ ✓, $0.6 > 0.30$ ✓, $0.28 < 0.30$ ✗. Why does this decide it? the first $δ V$ under the threshold is where distributions collide.

Verify: QLC ( $b = 4$ ) is the first to overlap, since $0.28 V < 0.30 V$ while TLC's $0.6 V$ clears it. This is precisely why QLC leans hardest on Error Correction Codes (LDPC/BCH) — the raw margin is already below the smear budget.

The two-panel figure below shows exactly this: on the left, TLC's 8 bell-curve smears sit far enough apart (the double-arrow marks one $δ V = 0.6 V$ gap) that neighbouring curves barely touch at the base; on the right, QLC's 16 smears — same half-width $w$ but a $δ V$ of only $0.28 V$ — visibly bleed into each other. Where two curves overlap, a read cannot tell which level it landed in, which is the geometric meaning of "raw bit error."

Recall Quick self-test on the matrix

Forward $b \to δ V$ ::: $δ V = Δ V_{w in d o w} / (2^{b} - 1)$ ; count gaps as $L - 1$ . Inverse $δ V \to b$ ::: $2^{b} \leq Δ V_{w in d o w} / δ V + 1$ , then round down to a whole bit. Why does SLC never divide by zero but $b = 0$ does? ::: $b = 1$ gives $L - 1 = 1$ (one gap); $b = 0$ gives $L - 1 = 0$ (a cell storing nothing). Ratio of crowding between two types ::: $(2^{b_{1}} - 1) / (2^{b_{2}} - 1)$ — the window cancels. Capacity scaling at fixed die ::: linear in $b$ : QLC is $4 \times$ SLC data on the same cells. Gray guarantee ::: adjacent (one-level) misread flips exactly one bit; larger jumps flip more.

Connections

Multi-level cell (MLC - TLC - QLC) flash — the parent this page extends.
Threshold Voltage and ISPP Programming — where $δ V$ and reference voltages come from.
Error Correction Codes (LDPC/BCH) — cleans up the overlap errors of Ex 10.
Gray Code — the adjacency rule used in Ex 7.
SLC Cache and SSD Write Amplification — the mechanism behind Ex 9.
Wear Leveling and Flash Endurance — the endurance numbers of Ex 8.