Multi-level cell (MLC - TLC - QLC) flash: Visual walkthrough

We assume you have never seen a logarithm, a bell curve, or the word "threshold." Every symbol is earned before it is used.

Step 1 — What is actually stored: charge → a voltage

WHAT: We put some number of electrons onto that island. WHY: trapped charge changes how easily the transistor turns on. The voltage you must apply to the outside gate to make current flow is called the threshold voltage $V_{t h}$ — think of it as "how hard you have to push to switch the cell on."

PICTURE: More electrons on the island push $V_{t h}$ higher. So charge becomes a voltage number we can measure. That is the whole trick — an analog knob.

Figure — Multi-level cell (MLC - TLC - QLC) flash

$Q$ — the charge (number of electrons) on the floating gate; our input knob.
$V_{t h}$ — the threshold voltage it produces; our readable output.

Step 2 — The playground has a fixed fence: the voltage window

WHAT: $V_{t h}$ cannot be any value we like. There is a lowest usable value (empty gate, call it $V_{l o w}$ ) and a highest usable value (gate stuffed as full as physics and the read circuitry allow, $V_{hi g h}$ ).

WHY this matters: the useful span $Δ V_{w in d o w} = V_{hi g h} - V_{l o w}$

$Δ V_{w in d o w}$ — the total width of the playground, in volts. The Greek $Δ$ ("delta") just means "difference / span."
$V_{hi g h}, V_{l o w}$ — the top and bottom fences.

This width is fixed by the silicon. We do not get more room by wanting more bits. Every level we invent must fit inside this same fence. Hold that thought — it is the source of all the pain later.

PICTURE: a horizontal voltage axis with two walls. Everything from here lives between those walls.

Step 3 — Slice the window into $L$ levels; count the bits

WHAT: Instead of asking "gate empty or full?" (2 states), we agree on $L$ distinct target voltages inside the window — call them levels. Each level is a codeword.

WHY $lo g_{2}$ enters here — and not some other tool: we need to answer "how many yes/no facts (bits) does choosing 1-of- $L$ levels carry?" One bit is one yes/no choice, which splits possibilities in half. Two bits give $2 \times 2 = 4$ choices, three bits give $2 \times 2 \times 2 = 8$ . So $b$ bits select among $2^{b}$ things: $L = 2^{b}$

$L$ — number of levels (choices).
$b$ — number of bits per cell.
the $2$ — because each bit doubles the count (binary = two options each).

To go the other way — "given $L$ levels, how many bits?" — we need the function that undoes raising 2 to a power. That undoer is $lo g_{2}$ ("log base two"), literally the question "2 to what power gives $L$ ?": $b = lo g_{2} L$

That is the only reason a logarithm appears: it is the inverse of the doubling.

PICTURE: the window from Step 2, now cut by evenly spaced tick marks. 2 ticks = SLC (1 bit), 4 = MLC (2 bits), 8 = TLC (3 bits), 16 = QLC (4 bits).

Recall Check the log

$lo g_{2} 8 = ?$ ::: $3$ , because $2^{3} = 8$ — TLC stores 3 bits.

Step 4 — Fenceposts: why the spacing divides by $L - 1$ , not $L$

WHAT: We want the spacing $δ V$ between two neighbouring level centres.

WHY $L - 1$ : place $L$ dots along a line. The gaps between them number one fewer than the dots. 2 fences → 1 gap; 4 fenceposts → 3 gaps. This is the fencepost rule. The level centres are the posts; the spacings are the gaps. The bottom post sits at $V_{l o w}$ , the top post at $V_{hi g h}$ , and the whole window $Δ V_{w in d o w}$ is split into $L - 1$ equal pieces: $δ V \approx \frac{Δ V _{w in d o w}}{L - 1} = \frac{Δ V _{w in d o w}}{2 ^{b} - 1}$

$δ V$ — voltage gap between adjacent level centres; the "breathing room."
$L - 1 = 2^{b} - 1$ — the number of gaps (fencepost rule, then $L = 2^{b}$ substituted).

PICTURE: four posts, three labelled gaps — literally count them so the $- 1$ is undeniable.

Step 5 — Crank the handle: how $δ V$ collapses SLC→QLC

WHAT: plug $b = 1, 2, 3, 4$ into $2^{b} - 1$ and read off the gap counts.

Type	$b$	$L = 2^{b}$	gaps $= 2^{b} - 1$	$δ V$ share
SLC	1	2	1	$Δ V_{w in d o w} /1$
MLC	2	4	3	$Δ V_{w in d o w} /3$
TLC	3	8	7	$Δ V_{w in d o w} /7$
QLC	4	16	15	$Δ V_{w in d o w} /15$

WHY exponential, not linear: each extra bit doubles $L$ , so the denominator roughly doubles too ( $1 \to 3 \to 7 \to 15$ ). The gap does not shrink by a fixed subtraction — it shrinks by a factor each step. Comparing the extremes: $\frac{δ V _{Q L C}}{δ V _{S L C}} = \frac{2 ^{1} - 1}{2 ^{4} - 1} = \frac{1}{15} \approx 0.067$ QLC's breathing room is ~15× narrower than SLC's.

PICTURE: four stacked axes (SLC, MLC, TLC, QLC), same total width, the tick marks visibly jamming together as you descend.

Step 6 — Levels are smears, not points (the reliability twist)

WHAT: a programmed level is never one exact voltage. Program noise, cell interference, and slow charge leakage spread it into a bell-curve smear — a hump centred on the target, wide at the base.

WHY this is the whole story: reading means "is $V_{t h}$ above or below a reference line placed in the gap?" If two neighbouring smears overlap, some cells land on the wrong side and read as the wrong level → a raw bit error. Fixed smear width, shrinking $δ V$ ⇒ overlap grows fast.

PICTURE: SLC — two fat humps with a wide moat between them (no overlap). QLC — sixteen humps shoulder-to-shoulder, skirts overlapping (shaded error region). This is why Error Correction Codes (LDPC/BCH) and read retries are mandatory for TLC/QLC, and why Threshold Voltage and ISPP Programming fights to keep each smear as thin as possible.

Step 7 — Degenerate & edge cases (never leave the reader stranded)

Definition Cover every corner

$b = 1$ (SLC): $2^{b} - 1 = 1$ , so $δ V = Δ V_{w in d o w}$ — the entire window is one giant gap. Maximum safety. This is the baseline, not a special case.
$b = 0$ (no bits): $L = 2^{0} = 1$ level. One level = no choice = stores nothing. The formula $δ V = Δ V_{w in d o w} / (2^{0} - 1) = Δ V_{w in d o w} /0$ divides by zero — correctly signalling "there are no gaps because there's only one post." A degenerate, non-storing cell.
Very large $b$ (PLC and beyond): $2^{b} - 1$ explodes; $δ V \to$ smaller than the smear width, so smears always overlap → error rate too high to correct → not manufacturable. The formula tells you the wall before physics does.
Uneven windows (reality): real levels are not equally spaced — makers widen error-prone gaps and shrink safe ones. Our even-split $δ V$ is the honest average; treat it as the typical case, not a promise every gap is identical.

PICTURE: three mini-panels — the $b = 1$ single-gap window, the $b = 0$ single-post "nothing", and the PLC smears fully merged into mush.

Step 8 — Label the levels smartly: Gray code

WHAT: once we have $L$ levels we must name each with a bit pattern. The obvious plain-binary order ( $000, 001, 010, \dots$ ) sometimes flips two bits between neighbours (e.g. $001 \to 010$ ).

WHY Gray code: the most likely misread is into an adjacent level (skirts touch). If we order the codes so adjacent levels differ in exactly one bit, a one-level slip costs only one flipped bit — the smallest, easiest-for-ECC damage. See Gray Code.

TLC Gray order (each neighbour differs by one bit): 000 → 001 → 011 → 010 → 110 → 111 → 101 → 100

PICTURE: eight TLC levels along the axis, Gray labels underneath, the single changing bit highlighted between each pair.

The one-picture summary

Everything at once: charge sets $V_{t h}$ (Step 1) inside a fixed window (Step 2); we slice it into $L = 2^{b}$ levels (Step 3); the fenceposts leave $L - 1$ gaps so $δ V = Δ V_{w in d o w} / (2^{b} - 1)$ (Step 4–5); each level is a smear, and shrinking $δ V$ makes smears overlap → errors (Step 6); Gray labels keep a slip to one bit (Step 8).

Recall Feynman retelling of the whole walkthrough

Picture a shelf of fixed length (the voltage window). You want to mark spots on it and read data by which spot a marble rolled to. If you mark just 2 spots (SLC), they're far apart — even a shaky hand still lands you clearly on one. Mark 16 spots (QLC) on the same shelf and they're jammed together; the marble's wobble (the smear) means it often lands between two spots and you can't tell which you meant. Counting spots: $b$ yes/no marks give $2^{b}$ spots, and reading spots back is $lo g_{2}$ . The gaps between spots number one fewer than the spots (fencepost), so each gap gets $1/ (2^{b} - 1)$ of the shelf — that's why 16 spots feel 15× tighter than 2. Since the wobble stays the same size, tighter spots = more mistakes, so you add spell-check (ECC) and label the spots in Gray order so a one-spot slip is a one-letter typo, not two. More storage, more mistakes, more effort — the eternal flash bargain.

Connections

NAND Flash Architecture — where the floating gate physically lives.
Threshold Voltage and ISPP Programming — how each smear is placed tightly.
Error Correction Codes (LDPC/BCH) — cleans the overlap errors of Step 6.
Wear Leveling and Flash Endurance — wear widens the smears over time.
SLC Cache and SSD Write Amplification — the speed workaround.
Gray Code — the labelling of Step 8.