Exercises — Multi-level cell (MLC - TLC - QLC) flash

WHAT: convert levels → bits with $b={\log }_{2}L$. WHY that tool: ${\log }_2$ is the exact question "2 to the what power gives 8?" — it undoes the exponent in $L=2^b$. $b={\log }_{2}8=3(\text{because }{2}^3=8)$ Three bits per cell is called TLC (Triple-Level Cell).

$L=2^4=16,L-1=15$ WHY $L-1$: the guard bands are the gaps between the buckets. With 16 fence posts you get 15 gaps (fencepost rule) — the same reason a 4-rung ladder has 3 spaces between rungs.

WHAT: split the window evenly across the gaps. $L=2^3=8,L-1=7,\delta V=\frac{4.2}{7}=0.6\text{ V}$ WHY divide by 7 not 8: the level centres span the window; between 8 centres there are 7 intervals. Look at s01 — count the gaps, not the bars.

$L=16,L-1=15,\delta V=\frac{4.2}{15}=0.28\text{ V}$ Shrink factor vs TLC: $\frac{\delta V_{TLC}}{\delta V_{QLC}}=\frac{0.6}{0.28}=\frac{15}{7}\approx 2.14$ Meaning: the same charge-leakage smear now eats more than double the fraction of each gap. See s02 — the QLC point sits far below the TLC point, showing how fast the spacing collapses.

Capacity $=N\times b$. $\text{SLC: }5\times 10^{11}\times 1=5\times 10^{11}\text{ bits}$ $\text{QLC: }5\times 10^{11}\times 4=2\times 10^{12}\text{ bits}$ WHY linear: each cell independently holds $b$ bits, and there are $N$ of them — multiply. QLC gives 4× the data on the same silicon, the entire commercial reason it exists. (See SLC Cache and SSD Write Amplification.)

WHAT: take the ratio of the two margins. $\frac{\delta V_{SLC}}{\delta V_{QLC}}=\frac{\Delta V_{window}/(2^1-1)}{\Delta V_{window}/(2^4-1)}=\frac{2^4-1}{2^1-1}=\frac{15}{1}=15$ WHY the window cancels: both cells share the same physical window, so $\Delta V_{window}$ appears in numerator and denominator and drops out. The crowding is purely about how many gaps you carve — a geometric fact, independent of the voltage value. QLC has 15 gaps where SLC has 1, so each gap is $1/15$ as wide.

Relative margin $=\frac{\delta V_b}{\delta V_{SLC}}=\frac{2^1-1}{2^b-1}=\frac{1}{2^b-1}$.

The claim is false. Halving would give $1,\frac{1}{2},\frac{1}{4},\frac{1}{8}$. Reality falls faster than that early on ($1\to \frac{1}{3}$ is worse than halving) because the denominator $2^b-1$ grows exponentially, not by a fixed factor. The loss is not a subtraction and not a clean halving — it is governed by $\frac{1}{2^b-1}$.

One-level slip (110 → 010): compare bit by bit — only the leftmost bit changes ($1\to 0$). 1 bit flips. WHY that is the whole point of Gray code: adjacent levels are the ones whose voltage smears touch and get confused, so we designed them to differ in exactly one bit — the minimum possible, easiest for ECC to repair. (See Gray Code and Error Correction Codes (LDPC/BCH).)

Two-level jump (110 → 011): compare — bits change at position 1 ($1\to 0$) and position 3 ($0\to 1$). 2 bits flip. Gray code only guarantees single-bit difference for neighbours; a two-level jump can flip more. That is why keeping the physical smear inside one gap (good margin) matters even with Gray coding.

Lifetime (days) ≈ endurance cycles, so divide by 365 for years. $\text{SLC: }\frac{10^5}{365}\approx 274\text{ years}$ $\text{QLC: }\frac{10^3}{365}\approx 2.74\text{ years}$ Ratio: $10^5/10^3=100\times$ longer for SLC. Physical reason: every erase tunnels electrons through the oxide, slowly damaging it and widening the smear. QLC starts with almost no margin ($\delta V$ is $1/15$ of SLC's), so tiny oxide wear pushes smears into overlap far sooner → far fewer safe cycles. (See Wear Leveling and Flash Endurance.)

WHAT: time = data ÷ rate. $t_{QLC}=\frac{2000}{40}=50\text{ s},t_{SLC}=\frac{2000}{250}=8\text{ s}$ Speedup: $50/8=6.25\times$ faster to accept the burst. WHY this works: SLC mode has only 2 levels, so its target distributions are wide — ISPP needs far fewer verify pulses (see Threshold Voltage and ISPP Programming). The drive absorbs the burst fast, then migrates the data to dense QLC later while idle. The cost is later write-amplification when migrating. (See SLC Cache and SSD Write Amplification.)

WHAT: the margin must satisfy $\delta V\ge 4\sigma$. $4\sigma =4\times 0.05=0.2\text{ V (minimum allowed spacing)}$ Solve for the largest $L$ whose spacing still meets it: $\delta V=\frac{4.2}{L-1}\ge 0.2⟹L-1\le \frac{4.2}{0.2}=21⟹L\le 22$ Now $L$ must be a power of two, $L=2^b$. The largest power of two $\le 22$ is $16=2^4$. $\boxed{b_{max}=4\text{ (QLC)}}$ Check $b=5$ (PLC): $L=32$, $L-1=31$, $\delta V=4.2/31=0.135\text{ V}<0.2\text{ V}$ → fails. So this process cannot safely do PLC. WHY this is the whole game: cell design is a fight between the fixed window, the fixed smear width $\sigma$, and how greedily you slice. Every extra bit doubles $L$, and $\delta V\propto 1/(2^b-1)$ falls off a cliff — eventually crossing below the smear-driven floor. See s02 for the visual crossover.

Usable bits per cell $=$ (raw bits per cell) × (1 − ECC overhead). $\text{TLC: }3\times (1-0.10)=3\times 0.90=2.70\text{ usable bits}$ $\text{QLC: }4\times (1-0.25)=4\times 0.75=3.00\text{ usable bits}$ QLC still wins with 3.00 vs 2.70 usable bits/cell — but the gap ($3.00/2.70\approx 1.11$, only $11\%$) is far smaller than the raw $4/3\approx 33\%$ headline. Insight: the reliability tax (bigger ECC, from Error Correction Codes (LDPC/BCH)) quietly erodes much of QLC's density advantage. If QLC's overhead ever exceeded $32.5\%$, TLC would win — solve $4(1-x)=2.70\Rightarrow x=0.325$.