Metastability and synchronizers — Hinglish notes

3.4.13 · Hardware › Sequential Circuits

1. Metastability KYA hai?

2. Yeh kitne time tak stuck rehta hai? — Resolution law derive karo

Hum $t$ time baad abhi bhi metastable rehne ki probability first principles se derive karte hain.

Step 1 — Resolving loop ko model karo. Ek flip-flop ka output stage cross-coupled inverters ki ek pair hai: ek loop jisme gain $A > 1$ hai aur ek node capacitance $C$ / resistance $R$ hai, jo time constant $τ = R C / (A - 1)$ deta hai. Yeh step kyun? Regenerative loop kisi bhi tiny imbalance $v$ ko metastable point se exponentially amplify karta hai — yahi eventually state resolve karta hai.

Step 2 — Exponential departure. Balance point ke paas voltage deviation is tarah badhti hai: $v (t) = v_{0} e^{t / τ} .$ Yeh step kyun? Positive feedback ⇒ growth exponential hai, aur $τ$ speed set karta hai. Valid logic level $V_{L}$ tak pahunchne ke liye $v (t) \geq V_{L}$ chahiye, yaani resolution time $t = τ ln (V_{L} / v_{0})$ .

Step 3 — Chhota $v_{0}$ kitna likely hai? Initial imbalance $v_{0}$ is par depend karta hai ki data edge sampling instant ke kitni close aayi. Ek tiny window $Δ t$ ke andar aana uniformly likely hai, aur $v_{0} \propto Δ t$ . Flip-flop ke per clock metastable window mein enter karne ka chance hai: $P_{e n t er} = T_{0} \cdot f_{c l k} \cdot f_{d a t a},$ jahan $T_{0}$ device ka "susceptibility window" constant hai. Yeh step kyun? Ek clock edge (rate $f_{c l k}$ ) aur ek data change (rate $f_{d a t a}$ ) dono ko nearly coincide karna hoga; near-coincidence ki probability dono rates aur window width $T_{0}$ ke saath scale hoti hai.

Step 4 — Combine karo: slack $t$ ke baad abhi bhi metastable rehne ki probability. $P (fail) = T_{0} f_{c l k} f_{d a t a} e^{- t / τ}$ Yeh step kyun? $\propto T_{0} f_{c l k} f_{d a t a}$ probability se enter karo; time $t$ tak survive karo $e^{- t / τ}$ probability se (Step 2 se, zyada resolving time ⇒ abhi bhi stuck rehne ki exponentially kam probability).

3. Synchronizer kyun/kaise kaam karta hai

$t_{r} = T_{c l k} - t_{s u} - t_{p d}$

Kaise kaam karta hai: Agar FF1 metastable ho jaata hai, toh FF2 ke dekhne se pehle settle hone ke liye almost poora clock period milta hai. Ek bada $t_{r}$ exponential $e^{t_{r} / τ}$ mein plug karo toh MTBF years/centuries tak blow up ho jaata hai. Teesra FF add karna ek aur poora period add karta hai → ek aur exponential factor.

Figure — Metastability and synchronizers

4. Common mistakes (Steel-man + fix)

Recall Feynman: 12-saal ke bachche ko explain karo

Socho ek light switch hai jise ON ya OFF flick kiya ja sakta hai. Agar aap ise super gently exact middle mein tap karo, toh yeh halfway stuck ho sakta hai — light weirdly flicker karti hai aur aap bata nahi sakte ki on hai ya off. Woh "middle mein stuck rehna" hi metastability hai. Hum halfway-tap ko tab nahi rok sakte jab koi ise random time par flip karta hai. Isliye hum wait karte hain: pehle wale ke baad ek doosra switch lagate hain jo kuch time baad pehle wala copy karta hai. Tab tak pehla switch almost hamesha puri tarah ON ya OFF ho chuka hota hai, toh doosra switch ek clean answer copy karta hai. Zyada wait karo (zyada switches) = almost kabhi galat nahi.

Connections

D Flip-Flop — woh bistable element jo metastable hota hai
Setup and Hold Time — woh violated constraint jo ise trigger karta hai
Clock Domain Crossing (CDC) — real-world mein main cause
FIFO Design — domains ke across synchronized Gray-code pointers use karta hai
Positive Feedback and Regeneration — exponential resolution ki physics
Timing Analysis — jahan slack $t_{r}$ compute hota hai

Flashcards

Metastability kya hai?

Ek temporary knife-edge state jahan flip-flop output valid logic levels ke beech baith jaata hai aur resolution time unbounded (probabilistic) hota hai, jo setup/hold violation se hoti hai.

Flip-flop metastability mein kyun jaata hai?

Clock edge ke around setup/hold window ke andar data change, typically ek asynchronous / cross-clock-domain signal se.

MTBF formula likhо.

MTBF = \frac{e ^{t_{r} / τ}}{T _{0} f _{c l k} f _{d a t a}}

MTBF resolution time

t_{r}

ke saath exponentially kyun badhta hai?

Regenerative loop imbalance ko

e^{t / τ}

ki tarah drive karta hai, toh abhi bhi metastable rehne ki probability

e^{- t_{r} / τ}

ki tarah girती hai; reciprocal (MTBF)

e^{t_{r} / τ}

ki tarah badhta hai.

τ

physically kya hai?

Flip-flop ka regeneration time constant

τ = R C / (A - 1)

cross-coupled inverter loop se; chhota

τ

zyada jaldi resolve karta hai.

Two-FF synchronizer kaise help karta hai?

Yeh FF1 ko almost poora ek clock period (

t_{r} = T_{c l k} - t_{s u} - t_{p d}

) deta hai FF2 ke sample karne se pehle resolve hone ke liye, propagated failures ko astronomically rare banata hai.

Kya synchronizer metastability eliminate karta hai?

Nahi — FF1 abhi bhi metastable ho sakta hai; yeh sirf downstream logic tak pahunchne ki probability ko negligibly small (huge MTBF) banata hai.

Faster clocks metastability ko kyun worse banate hain?

Zyada

f_{c l k}

failure prefactor badhata hai AUR

t_{r}

ghataata hai, aur MTBF

\propto e^{t_{r} / τ}

rapidly collapse ho jaata hai.

Fan-out se pehle signal ko sirf ek baar synchronize kyun karo?

Same async edge par do alag synchronizers alag values par resolve ho sakte hain, inconsistent state create karte hain.

2-FF synchronizer ke liye resolution-time expression do.

t_{r} = T_{c l k} - t_{s u} - t_{p d}