Synchronous vs asynchronous counters — Hinglish notes

3.4.8 · Hardware › Sequential Circuits

Ek counter flip-flops ki chain hoti hai (usually T ya JK) jo binary states ka ek sequence cycle karti hai, har clock pe ek step. Dono families mein SIRF yahi fark hai ki har flip-flop ko apna clock kaise milta hai.

The Core Question

Ripple counter count kyun karta hai?

Ise ek single flip-flop se derive karte hain. T flip-flop with $T = 1$ use karo (har clock edge pe toggle). Uski output ko $Q$ kaho.

Agar $Q$ apne clock ki har falling edge pe toggle karta hai, toh $Q$ ek wave produce karta hai jo apne clock ki aadhi frequency par hoti hai. Ye key fact hai:

$f_{out} = \frac{f _{clk}}{2}$

Kyun? Ek poora output cycle (0→1→0) ko do toggles chahiye, aur har toggle ke liye ek clock edge chahiye. Toh do clock edges = ek output cycle ⇒ frequency aadhi ho jaati hai.

Ab inhe chain karo: $Q_{0}$ ko FF1 ke clock mein feed karo, $Q_{1}$ ko FF2 ke clock mein feed karo…

$f_{0} = \frac{f}{2}, f_{1} = \frac{f}{4}, f_{2} = \frac{f}{8}, \dots, f_{k} = \frac{f}{2 ^{k + 1}}$

$Q_{2} Q_{1} Q_{0}$ ko ek binary number ki tarah padho aur ye $0, 1, 2, \dots$ count karta hai — yahi ek divide-by- $2^{n}$ ripple counter hai ( $n$ flip-flops ke liye).

Figure — Synchronous vs asynchronous counters

Ripple counters slow kyun hote hain (propagation problem)

Har flip-flop ka ek delay $t_{p d}$ hota hai — clock edge aane aur uski output settle hone ke beech. Ripple counter mein edges sequence mein aate hain, toh delays add up ho jaate hain.

Synchronous counters fast kyun hote hain

Wahi clock har flip-flop ko feed karo. Ab har FF parallel mein settle hota hai, toh total delay sirf ek $t_{p d}$ hoti hai (plus AND-gate delay jo compute karta hai ki har FF ko kab toggle karna chahiye).

Lekin agar saare clocks ek saath fire karein, toh har bit ko kaise pata chalega ki kab toggle karna hai? Hum toggle condition derive karte hain.

Worked Examples

Common Mistakes

Quick Compare

Feature	Asynchronous (ripple)	Synchronous
Clock source	cascaded ( $Q_{k - 1}$ )	common master clock
Settle delay	$n t_{p d}$	$\approx t_{p d}$
Glitches	yes (transient wrong states)	no
Hardware	simplest (no AND gates)	more gates
Max freq	$1/ (n t_{p d})$	$1/ (t_{p d} + t_{A N D})$

Recall Feynman: ek 12-saal ke bacche ko samjhao

Ek line mein khade bacchon ko imagine karo jिनके haath mein lights hain. Ripple version mein, baccha #1 apni light flip karta hai, aur tab bacche #2 ko poke karta hai, jo flip karke bacche #3 ko poke karta hai… Aakhri light bahut baad mein change hoti hai — kuch der ke liye row ek galat pattern dikhata hai. Synchronous version mein, ek teacher "ABHI!" chillata hai aur sablog ek saath flip karte hain, lekin har baccha ek rule follow karta hai "sirf tab flip karo jab mere daaye wale saare bacche ON hon." Same counting, koi galat flicker nahi, aur bahut tez.

Connections

T flip-flop aur JK flip-flop — toggling building block
Propagation delay — ripple slow kyun hai
Frequency division — ripple counter as $\div 2^{n}$
Carry lookahead — AND-tree jo sync counters ko fast banata hai
Modulo-N counters — counter ko jaldi reset karna
Clock skew — true synchronicity ka real-world dushman

#flashcards/hardware

Sync aur async counters mein ek defining difference kya hai?

Har flip-flop ko clock kaise milta hai — shared master clock (sync) vs pichle FF ki output se clocked hona (async/ripple).

Ripple counter mein flip-flop

k

ko kaun clock karta hai?

Pichle flip-flop ka output

Q_{k - 1}

(ya

\overline{Q_{k - 1}}

n-bit ripple counter ka worst-case settle time?

n \cdot t_{p d}

(delays series mein add hote hain).

n-bit ripple counter ki max clock frequency?

f_{m a x} = 1/ (n t_{p d})

Ripple counters transient galat values kyun dikhate hain?

Bits ek ke baad ek change hoti hain (staggered delays), toh beech ke real-lekin-galat states appear hoti hain = decoding glitches.

Synchronous up-counter mein bit

k

ke liye toggle logic kya hai?

T_{k} = Q_{0} Q_{1} \dots Q_{k - 1}

(saare lower bits ka AND — carry condition).

Synchronous counter ki max frequency n se independent kyun hai?

Saare FFs ek saath clock hote hain, toh total delay ek

t_{p d}

plus gate delay hai,

n t_{p d}

nahi.

T=1 wala ek single T flip-flop kaisi frequency output karta hai?

Apni clock frequency ki aadhi,

f /2

(do edges per output cycle).

Clock ko 8 se divide karne ke liye kitne flip-flops chahiye?

3, kyunki

2^{3} = 8

Kaun sa counter extra AND gates use karta hai aur kyun?

Synchronous — kyunki har bit ki toggle condition saare lower bits se compute karni padti hai.