Setup and hold time constraints — Hinglish notes

3.4.5 · Hardware › Sequential Circuits

WHAT are we constraining?

YEH KYUN EXIST KARTE HAIN: ek real flip-flop feedback loops (cross-coupled gates) se bana hota hai. Loop ko time chahiye input ko acquire karne aur usse ek stable state mein regenerate karne ke liye. Window violate karo → loop 0 aur 1 ke beech adha atak sakta hai = metastability.

The pipeline picture (deriving the constraints)

Do flip-flops ko combinational logic se separated ek pipeline mein consider karo:

FF1 --Q--> [ combinational logic ] --D--> FF2
  ^                                          ^
  |------------------ CLK --------------------|

Figure — Setup and hold time constraints

Data FF1 se ek clock edge par nikalta hai, logic se guzarta hai, aur FF2 par pahunchna chahiye agli edge se pehle (setup ke liye), lekin bahut jaldi nahi ki current edge disturb ho jaye (hold ke liye).

Deriving the SETUP constraint (from first principles)

KAISE: FF2 ke D par naye data ke arrival time ko track karo, agli clock edge ke relative.

Clock period $T$ maan lo. Launch edge time $0$ par hai; FF2 par capturing edge time $T$ par hai (abhi ke liye clock skew ignore karo).

Data FF1 ke Q par time = $t_{c q}$ par valid hota hai (worst case $t_{c q}^{ma x}$ ).
Yeh $t_{l o g i c}^{ma x}$ lene wale logic se guzarta hai. Yeh FF2 ke D par pahunchta hai: $t_{a r r i v e} = t_{c q}^{ma x} + t_{l o g i c}^{ma x}$
FF2 chahta hai ki D uski edge $T$ se $t_{s u}$ pehle stable ho, yaani arrival $\leq T - t_{s u}$ hona chahiye.

SUBTRACTION KYUN? Hume period ke last $t_{s u}$ seconds FF2 ki "keep-still" window ke liye reserve karne chahiye, taaki kuch abhi bhi wahan arrive na ho raha ho.

$t_{c q}^{ma x} + t_{l o g i c}^{ma x} + t_{s u} \leq T$

Deriving the HOLD constraint (from first principles)

DOOSRA CONSTRAINT KYUN? Setup worry karta hai ki data agli edge ke liye bahut late aa raha hai. Hold worry karta hai ki naya data bahut jaldi aa jaye aur us value ko corrupt kar de jo FF2 isi edge par latch karne ki koshish kar raha hai.

Time $0$ par wahi edge FF1 se launch karta hai aur FF2 par capture karta hai:

Edge ke baad FF1 ke Q par sabse tezi se possible change: $t_{c q}^{min}$ .
Logic se sabse fast path: $t_{l o g i c}^{min}$ (contamination delay).
Toh FF2 ka D edge ke baad $t_{c q}^{min} + t_{l o g i c}^{min}$ jitni jaldi change hona shuru ho sakta hai.
FF2 ko chahiye ki D edge ke baad $t_{h}$ tak stable rahe. Toh earliest change $\geq t_{h}$ hona chahiye:

$t_{c q}^{min} + t_{l o g i c}^{min} \geq t_{h}$

Adding clock skew

Maan lo capturing clock FF2 par launching clock se later pahunchta hai, skew $t_{s k e w}$ ke saath (positive = capture clock delayed).

Setup aasaan ho jaata hai (delayed capture edge se pehle zyada time): $T + t_{s k e w} \geq t_{c q}^{ma x} + t_{l o g i c}^{ma x} + t_{s u}$
Hold mushkil ho jaata hai (delayed edge keep-still window ko fast data tak extend kar deta hai): $t_{c q}^{min} + t_{l o g i c}^{min} \geq t_{h} + t_{s k e w}$

Worked Examples

Recall Feynman: explain to a 12-year-old

Imagine karo ki tum ek note apne dost ko pass kar rahe ho exactly jab teacher taali bajati hai. Agar tum note bahut late thelte ho, tumhara dost taali se pehle pakad nahi paata — woh garbage padh leta hai (setup problem: unhe note pehle do ya taali slow bajao). Agar tum note taali ke baad bahut jaldi wapas chheen lete ho, tumhara dost kabhi finish nahi kar paaya padna (hold problem: note ek moment aur pakdo — taali slow bajana help nahi karta, bas pakde rehna hota hai). Har taali ke around chhota sa "please note mat hilao" moment flip-flop ki keep-still window hai.

Flashcards

Setup time definition

Minimum time jitna data active clock edge se PEHLE stable rehna chahiye correct sampling ke liye.

Hold time definition

Minimum time jitna data active clock edge ke BAAD stable rehna chahiye.

Setup constraint formula

T \geq t_{c q}^{ma x} + t_{l o g i c}^{ma x} + t_{s u}

Hold constraint formula

t_{c q}^{min} + t_{l o g i c}^{min} \geq t_{h}

Kaun sa constraint max clock frequency limit karta hai?

Setup (isme

T

hota hai);

f_{ma x} = 1/ (t_{c q}^{ma x} + t_{l o g i c}^{ma x} + t_{s u})

Clock slow karna hold violation kyun fix nahi kar sakta?

Hold constraint mein koi

T

term nahi hai; yeh same-edge race hai, isliye period cancel ho jaata hai. Delay/buffers add karke fix karo.

Setup kaunse delays use karta hai?

Maximum (worst-case) delays:

t_{c q}^{ma x}

t_{l o g i c}^{ma x}

Hold kaunse delays use karta hai?

Minimum (contamination/fastest) delays:

t_{c q}^{min}

t_{l o g i c}^{min}

Positive capture-clock skew ka setup par effect?

Relax karta hai:

T + t_{s k e w} \geq t_{c q}^{ma x} + t_{l o g i c}^{ma x} + t_{s u}

Positive capture-clock skew ka hold par effect?

Tight karta hai:

t_{c q}^{min} + t_{l o g i c}^{min} \geq t_{h} + t_{s k e w}

Agar keep-still window violate ho jaaye toh kya hota hai?

Metastability — output 0 aur 1 ke beech unpredictably hover kar sakta hai.

t_{c q}

kya hai?

Clock-to-Q delay: clock edge se lekar Q ke naya value output karne tak ka time.

Hold violation kaise fix karein?

Fast (min-delay) combinational path par buffer/delay elements add karo.

Connections

Flip-Flops and Latches — woh storage element jiske yeh constraints describe hain.
Metastability — failure mode jab window violate ho jaati hai.
Clock Skew and Jitter — clock timing shifts constraints ko kaise affect karti hai.
Static Timing Analysis (STA) — saare paths mein setup/hold ki systematic checking.
Pipelining — jahan setup har stage ka $f_{ma x}$ set karta hai.
Combinational Logic Delay — $t_{l o g i c}^{ma x}$ aur $t_{l o g i c}^{min}$ ka source.