Demultiplexers: Worked examples — Hardware deep dive

This page is the practice arena for the DEMUX topic. We will hit every kind of question a DEMUX can throw at you — normal routing, the data-is-zero trap, the decoder-mode trick, MSB/LSB confusion, cascading, and a real-world word problem. First we map the terrain, then we walk each cell.

The scenario matrix

Every DEMUX question is one (or a blend) of these cells. The table below is our checklist — the examples that follow each say which cell they land in.

Cell	What makes it tricky	Covered by
A. Plain route	data $= 1$ , one clear destination	Ex 1
B. Data $= 0$ (degenerate)	destination chosen but nothing to deliver	Ex 2
C. Boundary codes $0$ and max	first output $Y_{0}$ and last output $Y_{2^{n} - 1}$	Ex 3
D. Decoder mode ( $D = 1$ fixed)	DEMUX behaving as a decoder	Ex 4
E. MSB/LSB flip (exam trap)	same bits read two ways give different outputs	Ex 5
F. Cascade / build big from small	two small DEMUX = one bigger DEMUX	Ex 6
G. Real-world word problem	translate a story into $D$ , selects, output	Ex 7
H. Reverse question	"which selects light $Y_{k}$ ?" — go backward	Ex 8

The count of outputs is always $2^{n}$ for $n$ selects. Keep that in your pocket.

Worked example Example 1 — Cell A: plain route (1-to-8 DEMUX)

A $1$ -to- $8$ DEMUX has $n = 3$ selects. Given $D = 1$ and $S_{2} S_{1} S_{0} = 011$ , which output is high?

Forecast: guess the output index before reading on — convert $011$ to decimal in your head.

Convert the select code to a number. $S_{2} S_{1} S_{0} = 011 = 0 \times 4 + 1 \times 2 + 1 \times 1 = 3$ . Why this step? The output index equals the decimal value of the selects — this instantly names the destination as $Y_{3}$ .
Write the minterm for $k = 3$ . Code $3$ is $S_{2} = 0, S_{1} = 1, S_{0} = 1$ , so $m_{3} = \overline{S_{2}} S_{1} S_{0}$ . Why this step? $m_{3}$ must be $1$ only at code $011$ ; each variable appears complemented where the bit is $0$ .
Apply the master rule. $Y_{3} = D \cdot m_{3} = 1 \cdot (\overline{0} \cdot 1 \cdot 1) = 1 \cdot (1 \cdot 1 \cdot 1) = 1$ . Every other $Y_{k} = 0$ because its minterm is $0$ here.

Verify: exactly one output is $1$ and its index ( $3$ ) matches the select decimal ( $3$ ). ✅

Worked example Example 3 — Cell C: the two boundary codes (1-to-4 DEMUX)

On a $1$ -to- $4$ DEMUX with $D = 1$ , evaluate the smallest code $S_{1} S_{0} = 00$ and the largest code $S_{1} S_{0} = 11$ . Confirm the first and last outputs behave.

Forecast: which outputs? Guess before computing.

Code $00$ (decimal $0$ ). $m_{0} = \overline{S_{1}} \overline{S_{0}} = \overline{0} \cdot \overline{0} = 1 \cdot 1 = 1$ , so $Y_{0} = D \cdot m_{0} = 1$ . Why this step? $Y_{0}$ is the "all-selects-zero" output — its minterm uses all complemented variables. This is the easy-to-forget corner.
Code $11$ (decimal $3$ ). $m_{3} = S_{1} S_{0} = 1 \cdot 1 = 1$ , so $Y_{3} = D \cdot m_{3} = 1$ . Why this step? $Y_{3}$ is the "all-selects-one" output — its minterm uses no complements at all. The other boundary.
Boundaries never overlap. At code $00$ only $Y_{0} = 1$ ; at code $11$ only $Y_{3} = 1$ . No code fires two outputs.

Verify: the four minterms $m_{0}, m_{1}, m_{2}, m_{3}$ are mutually exclusive and cover all $4$ codes — a complete, gap-free set (this is why Decoders and DEMUX outputs partition the input space). ✅

Worked example Example 4 — Cell D: DEMUX as a decoder (1-to-8,

$D = 1$ ) Tie $D = 1$ permanently on a $1$ -to- $8$ DEMUX and sweep the selects $S_{2} S_{1} S_{0}$ from $000$ to $111$ . Show it becomes a $3$ -to- $8$ decoder.

Forecast: with $D$ stuck at $1$ , what does each $Y_{k}$ reduce to?

Kill the data term. $Y_{k} = D \cdot m_{k} = 1 \cdot m_{k} = m_{k}$ . Why this step? Setting $D = 1$ removes the gating — each output is now purely its minterm, which is exactly a decoder output.
Spot-check code $101$ (decimal $5$ ). $m_{5} = S_{2} \overline{S_{1}} S_{0} = 1 \cdot \overline{0} \cdot 1 = 1 \cdot 1 \cdot 1 = 1$ , so $Y_{5} = 1$ , all others $0$ . Why this step? One concrete code proves the whole sweep: each of the $8$ codes lights exactly its own line.
Interpret. As the selects count $0 \to 7$ , the single high output walks $Y_{0} \to Y_{7}$ — the defining behaviour of a $3$ -to- $8$ line decoder. Same silicon, new job.

Verify: $8$ codes → $8$ outputs, each high once → a valid decoder truth table. This is realisation #1 from the parent note. ✅

Worked example Example 5 — Cell E: MSB/LSB flip (the classic exam trap)

The bits on the wires are $S_{1} = 1, S_{0} = 0$ , and $D = 1$ on a $1$ -to- $4$ DEMUX. A student reads them LSB-first as " $01$ " and answers $Y_{1}$ . Using the correct convention ( $S_{1}$ = MSB), find the true output and expose the mistake.

Forecast: $Y_{1}$ or $Y_{2}$ ? Commit to a guess.

State the convention. $S_{n - 1}$ is the MSB. Here $S_{1}$ (MSB, weight $2$ ) $= 1$ and $S_{0}$ (LSB, weight $1$ ) $= 0$ . Why this step? Value depends on which wire is worth more; you must fix this before converting.
Convert correctly. Value $= S_{1} \times 2 + S_{0} \times 1 = 1 \times 2 + 0 \times 1 = 2$ . So the true output is $Y_{2}$ . Why this step? Weighting each bit by its place value is the only correct decode.
The student's error. Reading LSB-first swaps the bits to " $01$ " $= 1$ , giving $Y_{1}$ — wrong. They multiplied $S_{0}$ by $2$ and $S_{1}$ by $1$ , i.e. flipped the weights.

Verify: compute $Y_{2} = D S_{1} \overline{S_{0}} = 1 \cdot 1 \cdot \overline{0} = 1$ ✅, while $Y_{1} = D \overline{S_{1}} S_{0} = 1 \cdot \overline{1} \cdot 0 = 0$ — the student's answer is genuinely $0$ , confirming they'd be wrong. ✅

Worked example Example 6 — Cell F: cascade two 1-to-4 into one 1-to-8

We only have

1

-to-

4

DEMUX chips (

2

selects,

4

outputs each) but need a

1

-to-

8

(

3

selects). Use the new top bit

S_{2}

to pick which chip gets the data. If

S_{2} S_{1} S_{0} = 110

, which of the eight outputs fires (

D = 1

Forecast: which chip, and which of its four lines?

Split the address. Look at the figure: $S_{2}$ feeds a $1$ -to- $2$ DEMUX that routes $D$ to either Chip A (when $S_{2} = 0$ ) or Chip B (when $S_{2} = 1$ ). The lower bits $S_{1} S_{0}$ then pick the line inside the chosen chip. Why this step? The MSB has weight $4$ — flipping it jumps the destination by $4$ , exactly the size of one chip's output block. So MSB = "which block", low bits = "which line in block".
Route by $S_{2}$ . $S_{2} = 1$ → data goes to Chip B, whose outputs are $Y_{4} \dots Y_{7}$ . Chip A's outputs $Y_{0} \dots Y_{3}$ receive $0$ . Why this step? The first-stage DEMUX gives $D$ to only one chip; the other chip sees data $= 0$ , so all its outputs are $0$ .
Route by $S_{1} S_{0}$ inside Chip B. $S_{1} S_{0} = 10 = 2$ , so Chip B's third line fires. Its outputs are $Y_{4}, Y_{5}, Y_{6}, Y_{7}$ , so line-index $2$ inside it is $Y_{4 + 2} = Y_{6}$ . Why this step? Output index $=$ (block base $4$ ) $+$ (in-block index $2$ ) $= 6$ , which matches $110 = 6$ directly.

Verify: $S_{2} S_{1} S_{0} = 110 = 6$ , and the cascade lit $Y_{6}$ . Whole-address decimal ( $6$ ) equals block-plus-offset ( $4 + 2 = 6$ ). ✅

Worked example Example 7 — Cell G: real-world word problem (memory row select)

A tiny memory has $8$ rows. A CPU sends a $3$ -bit row address $A_{2} A_{1} A_{0} = 100$ and a write-enable pulse that is currently $1$ . A $1$ -to- $8$ DEMUX distributes the write pulse to the correct row (see Memory Addressing). Which row's write line goes high?

Forecast: guess the row number.

Map the story onto DEMUX pins. Data input $D$ = the write-enable pulse $= 1$ . Select lines = the address $A_{2} A_{1} A_{0}$ . Outputs $Y_{0} \dots Y_{7}$ = the $8$ row-write lines. Why this step? A word problem is solved by naming which real signal is $D$ and which is the selects. Here the pulse is the thing being routed; the address chooses where.
Decode the address. $A_{2} A_{1} A_{0} = 100 = 1 \times 4 + 0 \times 2 + 0 \times 1 = 4$ . So $Y_{4}$ (row $4$ ) receives the pulse. Why this step? Same decimal-conversion habit — the address is the select code.
Check the others. All rows except row $4$ get $0$ , so no other row is accidentally written — vital, or data corrupts. $Y_{4} = D A_{2} \overline{A_{1}} \overline{A_{0}} = 1 \cdot 1 \cdot 1 \cdot 1 = 1$ .

Verify: exactly one row-write line high, index $4$ = address decimal $4$ . If the write-enable had been $0$ (no write happening), even row $4$ stays $0$ — the safe idle state. ✅

Worked example Example 8 — Cell H: the reverse question

On a $1$ -to- $16$ DEMUX ( $n = 4$ ), you observe that output $Y_{13}$ is the one carrying the data. What must the select lines $S_{3} S_{2} S_{1} S_{0}$ be, and what is $m_{13}$ ?

Forecast: convert $13$ to $4$ -bit binary first.

Decimal → binary. $13 = 8 + 4 + 1 = 1101$ , so $S_{3} S_{2} S_{1} S_{0} = 1101$ . Why this step? The reverse of "selects → output index" is "output index → selects". Break $13$ into powers of two: $8 (= S_{3}), 4 (= S_{2}), 0, 1 (= S_{0})$ . Check the weights: $1 \times 8 + 1 \times 4 + 0 \times 2 + 1 \times 1 = 13$ . ✅
Build the minterm. A bit that is $1$ appears plain, a bit that is $0$ appears complemented: $m_{13} = S_{3} S_{2} \overline{S_{1}} S_{0}$ . Why this step? The minterm must equal $1$ only at code $1101$ ; the single $0$ -bit ( $S_{1}$ ) is the one that gets the bar.
Sanity spot-check. Plug $S_{3} S_{2} S_{1} S_{0} = 1101$ : $m_{13} = 1 \cdot 1 \cdot \overline{0} \cdot 1 = 1 \cdot 1 \cdot 1 \cdot 1 = 1$ . Any other code makes at least one factor $0$ .

Verify: $16$ outputs need $n = 4$ selects ( $2^{4} = 16$ ), and $1101 = 13$ round-trips back to $Y_{13}$ . ✅

Recall

Recall Quick self-test

A 1-to-4 DEMUX has $S_{1} S_{0} = 01$ , $D = 1$ . Which output? ::: $Y_{1}$ (binary $01$ = decimal $1$ ). Output $Y_{6}$ of a 1-to-8 DEMUX fires — what are the selects? ::: $S_{2} S_{1} S_{0} = 110$ (since $6 = 110$ ). Why do all outputs go $0$ when $D = 0$ ? ::: Master rule $Y_{k} = D \cdot m_{k}$ ; a factor of $0$ zeroes every output. In a cascade, what does the MSB select? ::: Which sub-chip (output block) receives the data.

Connections

Demultiplexers — the parent topic these examples drill.
Decoders — Example 4 shows DEMUX-with- $D = 1$ is a decoder.
Minterms and SOP — every $m_{k}$ we built is a minterm.
Multiplexers — the mirror operation; compare "many-in-one-out".
Memory Addressing — Example 7's row-select DEMUX.
Bus Systems — routing one bus line to a chosen destination.
Encoders — the reverse-direction family member.