Exercises — Demultiplexers

Outputs: $2^n=2^3=8$. Data inputs: always exactly $1$. Why: Each output corresponds to one distinct binary code on the select lines. Three bits give $2^3=8$ different codes, hence 8 outputs. The "many" side of a DEMUX is the output side, never the input. Answer: 8 outputs, 1 data input.

(b) one input → many outputs. Why: Read the name — DEliver to MUltiple eXits. Option (a) describes a multiplexer, the mirror twin.

$Y_0=\overline{S}D{Y}_1=SD$ Why: $Y_0$ is chosen when $S=0$, and "$S=0$" is written $\overline{S}$ (read "NOT S", equals 1 when $S$ is 0). $Y_1$ is chosen when $S=1$, written plainly as $S$. In both, the data $D$ is ANDed in so the output only carries data when its line is selected.

Step 1 — decode the select. $S_1{S}_0=01=0\times 2+1\times 1=1$. So the destination is $Y_1$. Step 2 — confirm with the formula. $Y_1=D\overline{S_1}{S}_0=1\cdot \overline{0}\cdot 1=1\cdot 1\cdot 1=1$ All others have a minterm equal to 0, so they are 0. Answer: $Y_0=0,Y_1=1,Y_2=0,Y_3=0$.

$Y_1=D\overline{S_1}{S}_0=0\cdot 1\cdot 1=0$. Every output has $D$ as a factor, and $D=0$, so all outputs are 0. Lesson: The select lines pick where the data goes; the data decides what arrives. If no data ($D=0$), even the chosen door stays 0. The DEMUX never invents a 1.

Decode: $110=1\times 4+1\times 2+0\times 1=6$. So $Y_6$ is high. Confirm: $Y_6=D{S}_2{S}_1\overline{S_0}=1\cdot 1\cdot 1\cdot \overline{0}=1\cdot 1\cdot 1\cdot 1=1$. All others 0. Answer: $Y_6=1$.

Decode 5 into 3 bits: $5=101$, i.e. $S_2=1,S_1=0,S_0=1$. A bit that must be 1 appears plain; a bit that must be 0 appears barred: $Y_5=D{S}_2\overline{S_1}{S}_0$ Check: this equals 1 only when $S_2=1,S_1=0,S_0=1$ — exactly code 5. ✓

Compute $Y_0=\overline{S}D$ and $Y_1=SD$ row by row:

Read it: the data $D=1$ appears on exactly one output — $Y_0$ when $S=0$, $Y_1$ when $S=1$. Both zero-data rows give all zeros. This is the DEMUX contract, verified.

• If $D=1$: exactly one output is 1 (the selected one), because the select bits name exactly one code $k$ and only $m_k=1$. Arithmetic sum $=1$.
• If $D=0$: zero outputs are 1. Arithmetic sum $=0$. So the arithmetic sum $Y_0+Y_1+Y_2+Y_3=D$ always (here $+$ is ordinary addition of the four bit-values, not Boolean OR). The demux spreads but never duplicates or loses the data bit: the total is conserved and equals $D$.

Claim: for any select value, at most one minterm $m_k$ equals 1. Why: Each minterm $m_k$ is 1 only for the single binary code $k$. The select lines hold exactly one binary value at a time (each bit is either 0 or 1, no in-between in the logic model). That value equals exactly one code — call it $k^{\star }$. Therefore $m_{k^{\star }}=1$ and every other $m_k=0$. Since $Y_k=D\cdot m_k$, at most one $Y_k$ can be nonzero (and it carries $D$). ∎ Picture: think of the select value as a single arrow pointing at exactly one door among $2^n$; only that door can open.

Design move: tie the data input high, $D=1$, permanently. Then $Y_k=1\cdot m_k=m_k$ for every $k$ — the DEMUX outputs become the pure minterms, which is precisely what an $n$-to-$2^n$ decoder produces. For $k=5$: $5=101$, so $Y_5=m_5=S_2\overline{S_1}{S}_0$ which is 1 exactly when the 3-bit input is $101$ — the decoder's job. Same silicon, different role.

Structure (Figure 2 shows this exact wiring):

• Stage 1: one 1-to-2 DEMUX with data $D$, controlled by the MSB $S_1$. It produces two lines: $A_0=\overline{S_1}D$ and $A_1=S_{1}D$.
• Stage 2: two 1-to-2 DEMUXes, both controlled by the LSB $S_0$.
  • Feed $A_0$ into one: gives $Y_0=\overline{S_0}{A}_0$, $Y_1=S_0{A}_0$.
  • Feed $A_1$ into the other: gives $Y_2=\overline{S_0}{A}_1$, $Y_3=S_0{A}_1$.

Verify $S_1{S}_0=10$ (want $Y_2$): $A_1=S_{1}D=1\cdot D=D,A_0=\overline{S_1}D=0$ $Y_2=\overline{S_0}{A}_1=\overline{0}\cdot D=1\cdot D=D$ With $D=1$, $Y_2=1$; and since $A_0=0$, both $Y_0=Y_1=0$; and $Y_3=S_0{A}_1=0\cdot D=0$. Result: only $Y_2$ carries the data — matches the flat 1-to-4 DEMUX. ✓

The general form $Y_2=\overline{S_0}(S_{1}D)=D{S}_1\overline{S_0}$ is exactly the flat minterm expression, so the tree is equivalent.

Use a 1-to-4 DEMUX: data input = the serial line $D$; the 4 outputs are the load-enable lines of R0…R3. To load R3, drive the selects to $S_1{S}_0=11$ ($=3$). Then $Y_3=D{S}_1{S}_0=D$ reaches R3's enable; all other enables are 0, so only R3 captures the bit. This is exactly how address decoding steers data to one word.

Gate: a 2-input AND on each output — one input is the decoder line $m_k$, the other is the shared data $D$. Count: $2^4=16$ AND gates (one per output). Why it works: The decoder already computes every minterm $m_k$ (exactly one is 1). ANDing each with $D$ gives $Y_k=D\cdot m_k$ — the DEMUX equation. So DEMUX = decoder + one AND-with-$D$ per output, the parent note's realisation #1, generalised to $n=4$.

Set-up. Let the shared select value spell the code $k^{\star }$ (a specific number in $0,1,\dots ,2^n-1$). Let the letter $j$ below be a running index that ranges over every output number $j=0,1,\dots ,2^n-1$; it is the "counter" the MUX's summation walks through. DEMUX side: with data $D$ and select code $k^{\star }$, the outputs are $Y_k=D{m}_k$. Only $Y_{k^{\star }}=D$; the rest are 0. MUX side: a $2^n$-to-1 multiplexer with the same selects computes a Boolean OR over all output lines, each ANDed with its own minterm: $Z={\bigvee }_j(Y_j\wedge m_j)$ (here $\bigvee$ is Boolean OR, not arithmetic addition). Two facts collapse this sum:

• Orthogonality of minterms: $m_j\wedge m_{k^{\star }}=0$ whenever $j\ne k^{\star }$ (two different codes can't both be true at once), and $m_{k^{\star }}=1$ for the one matching code.
• Therefore every term with $j\ne k^{\star }$ is $0$, and only the $j=k^{\star }$ term survives: $Z=Y_{k^{\star }}\wedge m_{k^{\star }}=D\wedge 1=D$ So $Z=D$. The DEMUX fans the bit out onto line $k^{\star }$; the MUX with the same address funnels that exact line back. Together they are a selectable through-connection — the basis of routing data across a shared fabric.

Trace the active output for each select code (D=1):

• $S_1{S}_0=01(=1)\Rightarrow Y_1$ active.
• $S_1{S}_0=00(=0)\Rightarrow Y_0$ active (the intermediate glitch code).
• $S_1{S}_0=10(=2)\Rightarrow Y_2$ active.

So the active line jumps $Y_1\to Y_0\to Y_2$. The transient visit to code $00$ briefly pulses $Y_0$ even though the intended path never used it. Why: the two select bits do not change at the exact same instant (real wires have different delays). While they disagree, the DEMUX faithfully routes $D$ to whatever intermediate code the selects spell — a decoding glitch. In real designs an enable input (a global gate on $D$) is held low during select changes to suppress these pulses.

• 3 selects → 8 outputs, 1 data input.
• $Y_5=D{S}_2\overline{S_1}{S}_0$.
• arithmetic sum $Y_0+Y_1+Y_2+Y_3=D$ (data conserved, never duplicated).
• DEMUX with $D=1$ = decoder.
• DEMUX = decoder + one AND-with-$D$ per output.
• MUX-after-DEMUX (same selects) = transparent wire, $Z=D$.