Demultiplexers: Question bank — Hardware deep dive

True or false — justify

A DEMUX has many data inputs, just like a MUX.

False. A DEMUX has exactly ONE data input

D

and MANY outputs; the "many" side is the output side. The MUX is the mirror — many data inputs, one output.

A 1-to-8 DEMUX needs 8 select lines.

False. It needs

n = 3

select lines, because

2^{3} = 8

. The selects form a binary address, and

n

bits address

2^{n}

destinations, not

n

of them.

D = 0

, the selected output is still

1

because the select lines "turn it on."

False. Selects choose where the data goes, not what it is. The chosen output is

Y_{k} = D \cdot m_{k} = 0 \cdot 1 = 0

; a DEMUX never invents a

1

Every non-selected output floats to an undefined value in the pure logic model.

False. In the ideal logic model each non-selected output is driven hard to

0

, because its minterm

m_{k} = 0

forces

Y_{k} = D \cdot 0 = 0

. "Floating" only happens in real tri-state chips, not in the boolean model.

Tying

D = 1

turns a

1

-to-

2^{n}

DEMUX into an

n

-to-

2^{n}

decoder.

True. With

D = 1

each output becomes

Y_{k} = 1 \cdot m_{k} = m_{k}

, which is exactly a decoder's minterm output — same silicon, different job.

For a 1-to-2 DEMUX,

Y_{0} = \overline{S} D

and

Y_{1} = S D

are the complete equations.

True.

Y_{0}

fires only when

S = 0

(so

\overline{S}

) AND

D = 1

;

Y_{1}

only when

S = 1

AND

D = 1

. Each is the data ANDed with the "am I chosen?" condition.

Exactly one DEMUX output can be

1

at a time.

True (but conditional): at most one output is high. If

D = 1

exactly one is high; if

D = 0

zero outputs are high. Never two, because only one minterm

m_{k}

equals

1

for a given select code.

A DEMUX and a decoder are unrelated circuits.

False. A decoder computes the minterms

m_{k}

; a DEMUX ANDs each of those with

D

. Structurally, DEMUX = decoder + one AND gate per output.

The MUX equation and the DEMUX equation are the same formula read in opposite directions.

True. MUX:

Y = \sum_{k} D_{k} m_{k}

(many data collapse into one). DEMUX:

Y_{k} = D m_{k}

(one datum spreads to many). Same minterm machinery, reversed data flow.

Spot the error

"For a 1-to-4 DEMUX with

S_{1} S_{0} = 10

, the live output is

Y_{1}

Wrong.

S_{1} S_{0} = 10

means

1 \times 2 + 0 \times 1 = 2

, so the live output is

Y_{2}

, not

Y_{1}

. The error is reading the bits as if they were the decimal name, ignoring place value.

Y_{2} = D \overline{S_{1}} S_{0}

for a 1-to-4 DEMUX."

Wrong. Output

2

corresponds to code

S_{1} S_{0} = 10

, so

S_{1} = 1, S_{0} = 0

, giving

Y_{2} = D S_{1} \overline{S_{0}}

. The stated term is actually

Y_{1}

(code

01

"To route to output 5 on a 1-to-8 DEMUX, set

S_{2} S_{1} S_{0} = 011

Wrong.

011 = 3

, that routes to

Y_{3}

. Decimal

5

101

, so you need

S_{2} S_{1} S_{0} = 101

"A 1-to-2 DEMUX:

Y_{0} = S D

Wrong.

Y_{0}

must be high when

S = 0

, so it uses

\overline{S}

Y_{0} = \overline{S} D

. Writing

S D

swaps the two outputs.

"Since a DEMUX has

2^{n}

outputs, it must also have

2^{n}

select lines."

Wrong. Select lines and outputs are related exponentially, not equally:

n

selects →

2^{n}

outputs. Three selects give eight outputs.

"If two outputs of a working DEMUX are both

1

, the select value is ambiguous."

Wrong — a working DEMUX can never drive two outputs high. Two minterms can't be

1

at once. Two high outputs means a fault, not an ambiguous address.

Why questions

Why does each output need the data

D

ANDed into it, rather than just the minterm?

Because a DEMUX must transmit the data value, not merely point at a destination. The minterm alone (decoder) always outputs

1

at the chosen line; ANDing with

D

lets a

0

pass through as a

0

Why is exactly one minterm

m_{k}

ever equal to

1

for a given select code?

The minterms are built so each is

1

for one unique binary combination of the selects. Since the selects hold exactly one value at a time, only that one minterm matches; all others contain at least one flipped literal and become

0

Why do

n

select lines address exactly

2^{n}

outputs and not more or fewer?

Each select bit is a yes/no choice, doubling the number of distinguishable codes.

n

independent bits produce

2 \times 2 \times \dots = 2^{n}

distinct addresses, one per output.

Why can the same physical circuit act as both a DEMUX and a decoder?

Because a decoder is just a DEMUX with its data input frozen at

1

. Feeding

D = 1

makes

Y_{k} = m_{k}

, which is precisely a decoder's output — no rewiring, only a fixed input. See Decoders.

Why is the DEMUX central to Memory Addressing and Bus Systems?

One shared line (a bus wire, a write signal) must reach exactly one destination (a memory row, a peripheral). The DEMUX/decoder converts an address into a single "activate this one" line, gating the data to just that target.

Why is it wrong to picture a DEMUX as "storing" the routed value?

It's a combinational circuit — outputs are a pure instantaneous function of

D

and the selects. Change the inputs and the outputs change immediately; there is no memory element holding a previous value.

Edge cases

What happens to all outputs when

D = 0

, regardless of the select value?

Every output is

0

, since

Y_{k} = 0 \cdot m_{k} = 0

for all

k

. The selects still "point" somewhere, but there is nothing to deliver.

What is the smallest meaningful DEMUX, and what does it look like?

The 1-to-2 DEMUX with

n = 1

select line:

Y_{0} = \overline{S} D

Y_{1} = S D

. It is the base case from which all larger DEMUXes are built by adding select bits.

Is there a "1-to-1 DEMUX" (

n = 0

)? What would it do?

With zero select lines there is one output and no addressing choice, so

Y_{0} = D

always — the input just passes straight to the single output. It is a degenerate wire, not a useful router.

When both

D = 1

and the select code addresses an output, but the parent bus is also feeding another DEMUX with

D = 0

, what does each output line show?

Each DEMUX is independent: the

D = 1

DEMUX drives its selected line high, the

D = 0

DEMUX drives all its lines low. Outputs depend only on that chip's own

D

and selects, not on a neighbour.

If a select line is stuck (say

S_{0}

jammed at

1

), which outputs can the DEMUX still reach?

Only outputs whose code has

S_{0} = 1

— the odd-indexed ones (

Y_{1}, Y_{3}, \dots

). The even outputs become unreachable, because their minterms need

S_{0} = 0

, which can never occur.

Connections

Multiplexers — the mirror-twin; contrast the data-flow direction on every trap above.
Decoders — the $D = 1$ limiting case; several items hinge on this identity.
Minterms and SOP — why exactly one $m_{k}$ fires per code.
Memory Addressing — real-world stakes of the "one destination" rule.
Bus Systems — one line fanned to many, the physical DEMUX use.