XOR, NAND, NOR, XNOR gates: Worked examples — Hardware deep dive

This page is a drill ground. The parent note told you what each gate is. Here we hit every kind of question these gates can throw at you — every input combination, every degenerate case, a word problem, and an exam-style twist — and we work each one from line one.

Before we start: everything here uses only bits. A bit is either $0$ or $1$ . That's it. There are no other numbers in this whole page. When you see $A \cdot B$ it means AND, $A + B$ means OR, an overbar $\overline{A}$ means NOT (flip it), $\oplus$ means XOR, and $⊙$ means XNOR. Later we sometimes write two letters side by side, $A B$ — that is shorthand for the same AND, exactly like $A \cdot B$ ; the dot is just dropped to save space. If any of those still feel shaky, re-read AND, OR, NOT gates first — but we re-explain each as it appears.

The scenario matrix

Every question in this topic falls into one of these cells. Our examples below are labelled with the cell they cover, and together they fill the whole table.

Cell	What the case looks like	Why it can trip you
C1 — all-zero input	inputs $(0, 0)$	NOR "fires" here; easy to forget
C2 — all-one input	inputs $(1, 1)$	NAND fires here; XOR vs OR differ here
C3 — mixed input	inputs $(0, 1)$ or $(1, 0)$	XOR/XNOR flip here
C4 — degenerate: tie inputs together	both inputs same wire ( $A, A$ )	how NOT is born from NAND
C5 — degenerate: force one input to a constant	one input pinned to $0$ or $1$	gate collapses to a simpler gate
C6 — 3+ inputs / chaining	XOR of many bits	parity; associativity
C7 — algebraic identity (no numbers)	prove $\overline{A + B} = \overline{A} \overline{B}$	De Morgan direction
C8 — build a gate from NAND-only	multi-step wiring	order of operations
C9 — word problem	switches / alarms	translate words → gate
C10 — exam twist	"which gate is this circuit?"	reverse-engineer a truth table

Example 1 — All-zero input across all four gates · Cell C1

Example 2 — All-one input · Cell C2 (also the OR-vs-XOR trap)

Worked example Feed

$(1, 1)$ into all four gates. Forecast: three of these gates output $0$ here — but only one of those zeros is a genuine trap, a gate whose $(1, 1)$ output beginners routinely expect to be $1$ . Predict which gate that is before reading.

Step 1 — NAND $= \overline{1 \cdot 1} = \overline{1} = 0$ . Why? AND of $(1, 1) = 1$ (both are $1$ ), flipped $= 0$ . This is NAND's only low case.

Step 2 — NOR $= \overline{1 + 1} = \overline{1} = 0$ . Why? OR of $(1, 1) = 1$ (at least one is $1$ ), flipped $= 0$ .

Step 3 — XOR $= 1 \oplus 1 = 0$ . Why? Same inputs → not different → $0$ . This is the trap the forecast asked about: XOR agrees with plain OR on $(0, 1)$ and $(1, 0)$ , so beginners assume it agrees on $(1, 1)$ too — but OR $= 1$ while XOR $= 0$ . NAND and NOR also output $0$ here, yet nobody expects those to be $1$ (their whole job is to invert), so XOR is the one true "trap".

Step 4 — XNOR $= 1 ⊙ 1 = 1$ . Why? Same inputs → $1$ .

Verify: NAND $= 0$ , NOR $= 0$ , XOR $= 0$ , XNOR $= 1$ . Cross-check XOR vs plain OR at $(1, 1)$ : OR $= 1 \neq =$ XOR $= 0$ . ✅

Example 3 — Mixed input, both orders · Cell C3

Now that Examples 1–3 have filled every one of the four input rows, read them off the figure below. Each column is one gate; scan down its column and you are reading the exact numbers we just computed — the amber cells are the rows where that gate outputs $1$ . Notice the NAND column is all $1$ s except its bottom row, and the XOR and XNOR columns are perfect mirror images of each other, confirming the "opposite everywhere" sanity check.

Example 4 — Tie both inputs together · Cell C4

Worked example What does each gate become when you

wire both inputs to the same signal $A$ ? Forecast: guess before reading — which of the four collapse to a NOT gate, and which get stuck at a constant (never changing no matter what $A$ is)? Nail down your two-and-two split first.

Step 1 — NAND with tied inputs: $A \overline{\land} A = \overline{A \cdot A} = \overline{A}$ . Why? $A \cdot A = A$ — ANDing a bit with itself changes nothing (idempotence, see Boolean Algebra Laws). Overbar then gives $\overline{A}$ : a NOT gate. This is the trick that makes NAND universal.

Step 2 — NOR with tied inputs: $\overline{A + A} = \overline{A}$ . Why? $A + A = A$ (idempotence for OR). So NOR-with-tied-inputs is also a NOT gate — that's why NOR is universal too.

Step 3 — XOR with tied inputs: $A \oplus A = 0$ . Why? A bit is always the same as itself, never different, so XOR $= 0$ for every $A$ . It's stuck at constant $0$ .

Step 4 — XNOR with tied inputs: $A ⊙ A = 1$ (always same → constant $1$ ). Why? Same reason inverted: identical inputs are always "the same", so XNOR is stuck at constant $1$ .

Reconcile with the forecast: the split is two NOTs (NAND, NOR) and two constants (XOR $\to 0$ , XNOR $\to 1$ ). There is no buffer here — a buffer (an "output equals input, do-nothing" gate) would need a gate that copies $A$ unchanged, and none of these four does that when its inputs are tied. (You can get a buffer another way — e.g. two NOTs in series, or XOR-with-a-constant- $0$ from Example 5 — but not by tying inputs.) So if you forecast a buffer, correct it: tying inputs gives only NOTs and constants.

Verify: plug $A = 0$ : NAND $\to 1 = \overline{0}$ ✅, NOR $\to 1$ ✅, XOR $\to 0$ ✅, XNOR $\to 1$ ✅. Plug $A = 1$ : NAND $\to 0 = \overline{1}$ ✅, NOR $\to 0$ ✅, XOR $\to 0$ ✅, XNOR $\to 1$ ✅. Both values agree with the formulas, and the two "constant" gates genuinely ignore $A$ . ✅

The figure shows the NAND case wired out so you can see the single signal $A$ splitting into both input pins, then the bubble on the output producing $\overline{A}$ — trace the amber wire from the split, through the box, to the output label:

Example 5 — Pin one input to a constant · Cell C5

Before this example, one piece of shorthand: SOP stands for Sum Of Products. Don't let the arithmetic words fool you — here "product" just means an AND term (letters multiplied together) and "sum" means those terms ORed. So an SOP expression is a bunch of AND-groups joined by OR, like $\overline{A} B + A \overline{B}$ . We use it to turn a truth table into a formula (full method in Sum of Products (SOP)).

Worked example Force one input to a fixed value and let the other,

$A$ , vary. Cover all four gates for both constants ( $B = 1$ and $B = 0$ ). What simpler gate does each collapse to? Forecast: XOR with a constant- $1$ input is a hidden NOT — and XOR with a constant- $0$ is a hidden buffer. Predict the other three before reading.

Step 1 — XOR, $B = 1$ : $A \oplus 1 = \overline{A} \cdot 1 + A \cdot \overline{1} = \overline{A} + A \cdot 0 = \overline{A}$ → NOT. Why this step? Use the SOP form $\overline{A} B + A \overline{B}$ (the AND-terms-ORed formula for XOR), substitute $B = 1$ so $\overline{B} = 0$ . The second term dies, leaving $\overline{A}$ : a controllable inverter — a key idea in adders.

Step 2 — XOR, $B = 0$ : $A \oplus 0 = \overline{A} \cdot 0 + A \cdot \overline{0} = A$ → buffer (output equals input). Why? Now the first term dies and $\overline{0} = 1$ , leaving $A$ untouched. Combined with Step 1: XOR is a "flip if control $= 1$ , pass if control $= 0$ " switch.

Step 3 — XNOR, $B = 1$ : $A ⊙ 1 = \overline{A \oplus 1} = \overline{\overline{A}} = A$ → buffer. Why? XNOR is just the inverse of XOR, and from Step 1 $A \oplus 1 = \overline{A}$ ; inverting that gives $A$ back. XNOR, $B = 0$ : $A ⊙ 0 = \overline{A \oplus 0} = \overline{A}$ → NOT, because Step 2 gave $A \oplus 0 = A$ and we invert it. So XNOR's two constants are exactly XOR's two swapped.

Step 4 — NAND, $B = 1$ : $\overline{A \cdot 1} = \overline{A}$ → NOT ( $A \cdot 1 = A$ , identity law, then flip). NAND, $B = 0$ : $\overline{A \cdot 0} = \overline{0} = 1$ → stuck at $1$ , because $A \cdot 0 = 0$ always (AND with $0$ kills everything).

Step 5 — NOR, $B = 1$ : $\overline{A + 1} = \overline{1} = 0$ → stuck at $0$ ( $A + 1 = 1$ always). NOR, $B = 0$ : $\overline{A + 0} = \overline{A}$ → NOT, because $A + 0 = A$ (identity for OR), then flip.

Summary table (all four gates, both constants):

gate	$B = 0$ becomes	$B = 1$ becomes
XOR	buffer ( $A$ )	NOT ( $\overline{A}$ )
XNOR	NOT ( $\overline{A}$ )	buffer ( $A$ )
NAND	constant $1$	NOT ( $\overline{A}$ )
NOR	NOT ( $\overline{A}$ )	constant $0$

Verify: XOR $(A, 1)$ at $A = 0 \to 1, A = 1 \to 0$ ✅ (NOT). XOR $(A, 0)$ at $A = 0 \to 0, A = 1 \to 1$ ✅ (buffer). XNOR $(A, 1)$ at $A = 1 \to 1$ ✅ (buffer). NAND $(A, 0)$ at $A = 1 \to 1$ ✅ (constant $1$ ). NOR $(A, 0)$ at $A = 0 \to 1, A = 1 \to 0$ ✅ (NOT). Every cell of the table checks out. ✅

Example 6 — Chained XOR = parity · Cell C6

Example 7 — Algebraic identity, no numbers · Cell C7

Worked example Prove

$\overline{A + B} = \overline{A} \cdot \overline{B}$ (NOR equals AND-of-inverses) — De Morgan. Forecast: the bar does not distribute; it flips the operator ( $+$ becomes $\cdot$ ).

Step 1 — Build both sides' truth tables. Why? Two boolean expressions are equal iff they agree on all four input rows; there's nothing else to check.

$A$	$B$	$A + B$	$\overline{A + B}$	$\overline{A}$	$\overline{B}$	$\overline{A} \cdot \overline{B}$
0	0	0	1	1	1	1
0	1	1	0	1	0	0
1	0	1	0	0	1	0
1	1	1	0	0	0	0

Step 2 — Compare columns 4 and 7. They are identical: $1, 0, 0, 0$ . Why this proves it? Same output on every possible input = the same function. Done.

Verify: the wrong version $\overline{A} + \overline{B}$ would give $1, 1, 1, 0$ — different at rows $(0, 1)$ and $(1, 0)$ , so the "distribute the bar" instinct is provably false. ✅ (See Boolean Algebra Laws.)

Example 8 — Build XOR from NAND only · Cell C8

Worked example Verify the 4-NAND XOR circuit on

every input, then read it off the wiring figure. Let $\overline{\land}$ mean NAND. The circuit is $A \oplus B = (A \overline{\land} (A \overline{\land} B)) \overline{\land} (B \overline{\land} (A \overline{\land} B)) .$ Forecast: the two "same" inputs $(0, 0), (1, 1)$ must give $0$ ; the two "different" inputs $(0, 1), (1, 0)$ must give $1$ .

Let $N = A \overline{\land} B$ (the shared inner node feeding both branches), $T = A \overline{\land} N$ (top), $B o = B \overline{\land} N$ (bottom), and output $= T \overline{\land} B o$ .

Step 1 — $(0, 0)$ : $N = \overline{0 \cdot 0} = 1$ ; $T = \overline{0 \cdot 1} = 1$ ; $B o = \overline{0 \cdot 1} = 1$ ; out $= \overline{1 \cdot 1} = 0 = 0 \oplus 0$ . ✅ Why? Both inputs $0$ → the branches leave $N$ 's high value unmasked, and the final NAND of two $1$ s gives $0$ .

Step 2 — $(0, 1)$ : $N = \overline{0 \cdot 1} = 1$ ; $T = \overline{0 \cdot 1} = 1$ ; $B o = \overline{1 \cdot 1} = 0$ ; out $= \overline{1 \cdot 0} = 1 = 0 \oplus 1$ . ✅ Why? The differing input pulls the bottom branch to $0$ , so the final NAND has a $0$ input and outputs $1$ .

Step 3 — $(1, 0)$ : $N = \overline{1 \cdot 0} = 1$ ; $T = \overline{1 \cdot 1} = 0$ ; $B o = \overline{0 \cdot 1} = 1$ ; out $= \overline{0 \cdot 1} = 1 = 1 \oplus 0$ . ✅ Why? Mirror of Step 2 — now the top branch is pulled to $0$ .

Step 4 — $(1, 1)$ : $N = \overline{1 \cdot 1} = 0$ ; $T = \overline{1 \cdot 0} = 1$ ; $B o = \overline{1 \cdot 0} = 1$ ; out $= \overline{1 \cdot 1} = 0 = 1 \oplus 1$ . ✅ Why? Both inputs $1$ collapse $N$ to $0$ , both branches go high, final NAND gives $0$ .

Verify: all four outputs $0, 1, 1, 0$ = the XOR column exactly. This is the wiring used inside a Half Adder and Full Adder.

Trace it on the diagram: the amber input wires $A$ and $B$ both reach the shared gate N, whose output fans out (in cyan) to the top and bottom NANDs; those two branch gates then feed the single final NAND that emits $A \oplus B$ . Walk the $(1, 1)$ case along the wires — $N$ drops to $0$ , so both branch gates read a $0$ and go high to $1$ , and the final NAND of $(1, 1)$ swings the output back to $0$ , exactly matching $1 \oplus 1 = 0$ :

Example 9 — Word problem · Cell C9

Worked example A hallway light must be controllable from

two switches: flipping either switch toggles the light. Which single gate models the light, given the two switch positions $A, B \in {0, 1}$ ? Forecast: "either switch toggles it" is the definition of difference — think XOR.

Step 1 — Translate the requirement. Start with both switches down $(0, 0)$ , light OFF $(0)$ . Flip switch $A$ to $(1, 0)$ : light must turn ON $(1)$ . Why? "Flipping either switch toggles the light" forces a $0 \to 1$ change when exactly one input changes.

Step 2 — Continue the toggling. From $(1, 0)$ flip $B$ to $(1, 1)$ : light toggles back OFF $(0)$ . From $(1, 1)$ flip $A$ to $(0, 1)$ : toggles ON $(1)$ . Why? Each flip changes exactly one bit and must flip the output.

Step 3 — Collect the truth table: $(0, 0) \to 0, (0, 1) \to 1, (1, 0) \to 1, (1, 1) \to 0$ . That is exactly XOR. Why? Output is $1$ precisely when the two switches disagree — the hallmark of XOR.

Verify: at $(1, 1)$ XOR $= 0$ (light off), matching "both switches down or both up → light off." A real two-way staircase switch is literally an XOR of the two toggle states. ✅

Example 10 — Exam twist: reverse-engineer the gate · Cell C10

Worked example A mystery 2-input gate outputs

$1, 0, 0, 1$ for inputs $(0, 0), (0, 1), (1, 0), (1, 1)$ . Name it, give its Boolean expression, and say whether it is the inverse of any gate you know. Forecast: it fires on $(0, 0)$ and $(1, 1)$ — the "agree" rows. Guess XNOR.

Step 1 — Identify the firing rows. Output $= 1$ at $(0, 0)$ and $(1, 1)$ : the two rows where $A = B$ . Why? Reading a truth table always starts by listing the $1$ -rows — those become the SOP (AND-terms-ORed) terms.

Step 2 — Write SOP. $(0, 0) \Rightarrow \overline{A} \overline{B}$ ; $(1, 1) \Rightarrow A \cdot B$ (written compactly as $A B$ ). OR them: $f = A B + \overline{A} \overline{B} .$ Why SOP? Each $1$ -row contributes one AND term that is true only on that row; ORing them reproduces the table (method from Sum of Products (SOP)). Recall $A B$ is just $A \cdot B$ with the dot dropped.

Step 3 — Name it. This is the "same/equivalence" gate = XNOR $= A ⊙ B$ , and it is the inverse of XOR (whose table is $0, 1, 1, 0$ ). Why? Flip every bit of the XNOR column $1, 0, 0, 1$ and you get $0, 1, 1, 0$ = XOR. Opposite everywhere.

Verify: $f$ at $(0, 1) = 0 \cdot 1 + 1 \cdot 0 = 0$ ✅; at $(1, 1) = 1 \cdot 1 + 0 \cdot 0 = 1$ ✅. Column $1, 0, 0, 1$ reproduced. See Karnaugh Maps for simplifying such SOP forms and Universal Gates for building XNOR from NANDs. ✅

Recall Which cell was hardest for you?

Re-do the one you forecasted wrong. The classic misses are C2 (XOR vs OR at $(1, 1)$ ) and C7 (De Morgan direction).

Recall

Output of NOR only when...?

all inputs are

0

(Cell C1).

XOR of

(1, 1)

vs OR of

(1, 1)

XOR

= 0

, OR

= 1

(Cell C2).

Tie both NAND inputs to

A

gives...?

\overline{A}

, a NOT gate (Cell C4).

A \oplus 1

simplifies to...?

\overline{A}

(Cell C5).

A \oplus 0

simplifies to...?

A

— a buffer (Cell C5).

Chained XOR of

1, 1, 0, 1, 1

0

(four

1

s = even parity, Cell C6).

De Morgan:

\overline{A + B} =

\overline{A} \cdot \overline{B}

(Cell C7).

Gate with table

1, 0, 0, 1

XNOR,

A B + \overline{A} \overline{B}

(Cell C10).

Connections

XOR, NAND, NOR, XNOR gates — the parent this drill supports
3.1.06 XOR, NAND, NOR, XNOR gates (Hinglish) — Hinglish version
AND, OR, NOT gates — the primitives every example reduces to
Boolean Algebra Laws — idempotence, identity, De Morgan used throughout
Sum of Products (SOP) — Examples 5, 10 build expressions this way
Half Adder and Full Adder — XOR-from-NAND (Ex 8) is the sum-bit circuit
Parity Bits & Error Detection — chained XOR (Ex 6)
Karnaugh Maps — simplifying the SOP forms above
Universal Gates — why NAND alone builds everything (Ex 4, 8)