XOR, NAND, NOR, XNOR gates: Question bank — Hardware deep dive

Before the traps, the exact notation and words we lean on constantly, defined from zero so nothing is assumed:

What a "bubble" looks like on a real gate, and the four truth-table rows every two-input gate has:

Look at the left sketch: the plain AND gate (flat back, round nose) becomes a NAND the instant we glue the small circle — the bubble — onto its output. That bubble is the overbar made physical. The right sketch is the truth-table matrix: for two inputs there are exactly $2 \times 2 = 4$ rows — $(0, 0), (0, 1), (1, 0), (1, 1)$ — and every trap below refers to these four rows, so keep them in view.

Here are all five gates side by side across those four rows, so no trap forces you to rebuild a table in your head:

True or false — justify

TRUE or FALSE: NAND is just AND with a different name.

FALSE — NAND is AND with the output inverted (the bubble); its output is the exact opposite of AND on every one of the four rows, agreeing with AND nowhere.

TRUE or FALSE: NOR outputs

1

only when every input is

0

TRUE — NOR is

\overline{A + B}

; OR is

1

if any input is

1

, so its inverse is

1

only when nothing is

1

TRUE or FALSE: XOR and OR give the same result for two inputs.

FALSE — they agree on

(0, 0), (0, 1), (1, 0)

but split at

(1, 1)

: OR

= 1

(at least one), XOR

= 0

(they are the same, not different).

TRUE or FALSE: XNOR is the same as "both inputs are

1

FALSE — XNOR is

1

whenever inputs agree, which includes

(0, 0)

as well as

(1, 1)

; requiring both to be

1

would miss the

(0, 0)

case.

TRUE or FALSE: A single NAND gate can act as a NOT gate.

TRUE — tie both inputs together:

A NAND A = \overline{A \cdot A} = \overline{A}

, since

A \cdot A = A

by idempotence.

TRUE or FALSE: AND is universal because you can build NAND from it.

FALSE — AND alone can never produce an inverted output, so it cannot make NOT; without NOT it fails universality entirely.

TRUE or FALSE:

\overline{A + B} = \overline{A} + \overline{B}

FALSE — De Morgan flips the operator:

\overline{A + B} = \overline{A} \cdot \overline{B}

. The bar over a sum becomes a product of bars.

TRUE or FALSE: XNOR is the inverse of XOR, so

A ⊙ B = \overline{A \oplus B}

TRUE — "same" is the logical opposite of "different", so inverting the XOR output row-by-row gives exactly the XNOR table.

TRUE or FALSE: NOR is also universal, just like NAND.

TRUE — from NOR you can build NOT (tie inputs), then OR (NOR then NOT), then AND (invert inputs then NOR by De Morgan), so it makes all three basics.

TRUE or FALSE: Chaining XOR across many bits tells you the parity of the group.

TRUE — by associativity the chain is well-defined, and each additional

1

toggles the running result, so the final bit is

1

exactly when an odd number of

1

s was seen.

Spot the error

Claim: "

A NAND A = A

because

A \cdot A = A

." Where's the error?

The person stopped before inverting — NAND includes the bubble, so

A NAND A = \overline{A \cdot A} = \overline{A}

, not

A

Claim: "To build OR from NAND, just feed

A

and

B

straight into a NAND." Error?

That gives

\overline{A \cdot B}

(NAND), not OR. You must first invert each input, then NAND:

\overline{\overline{A} \cdot \overline{B}} = A + B

by De Morgan.

Claim: "XOR's SOP is

A B + \overline{A} \overline{B}

." Error?

Those are the same-input rows — that's XNOR. XOR uses the different rows:

\overline{A} B + A \overline{B}

Claim: "NAND of

(0, 0)

0

because both inputs are low." Error?

NAND outputs

0

only when all inputs are

1

; with

(0, 0)

the AND is

0

and its inverse is

1

, so NAND

(0, 0) = 1

Claim: "Since NAND is universal, a NAND gate is more physically complex than an AND gate." Error?

Backwards — a CMOS NAND is simpler (fewer transistors) than AND, which is literally a NAND followed by an inverter. Universality is about logic completeness, not part count.

Claim: "XNOR of

(1, 0)

1

because at least one input is

1

." Error?

That is OR-style reasoning. XNOR asks whether the inputs match;

(1, 0)

disagree, so XNOR

(1, 0) = 0

Claim: "

\overline{A \cdot B} = \overline{A} \cdot \overline{B}

, so NAND equals AND-of-inverses." Error?

De Morgan again:

\overline{A \cdot B} = \overline{A} + \overline{B}

(a sum, i.e. OR of inverses), not a product.

Why questions

Why does XOR sit at the heart of an adder's sum bit?

Adding two bits, the sum digit is

1

exactly when the inputs differ (

0 + 1

1 + 0

); that "difference detector" is precisely XOR — see Half Adder and Full Adder.

Why can inverting both inputs of a NAND produce OR but not AND?

Because

\overline{\overline{A} \cdot \overline{B}} = A + B

by De Morgan — inverting inputs before a NAND turns the internal AND into an OR. AND instead needs a NAND followed by a NOT.

Why is a gate that can only make AND and OR (but never NOT) not universal?

Every useful family of circuits needs the ability to invert; without NOT you cannot express complements, so whole classes of functions are unreachable.

Why does XOR detect odd parity rather than even?

XOR outputs

1

for a single (odd) mismatch and returns to

0

after a second

1

toggles it back; each

1

flips the state, so an odd count ends at

1

— the basis of Parity Bits & Error Detection.

Why do real chips flood the die with NAND (or NOR) cells instead of a mix of AND/OR/NOT?

One universal cell type can be etched identically billions of times and wired into any function, which is far cheaper to manufacture than several distinct cell designs.

Why is De Morgan the engine behind every NAND↔NOR↔basic conversion?

It is the one law that lets you move a bar across an operator, swapping AND for OR — every "build X from NAND" trick is a De Morgan rewrite from Boolean Algebra Laws.

Edge cases

If both inputs of a two-input XOR are the same, what is the output — and does this ever depend on whether they are

0

1

Output is always

0

for matching inputs, whether

(0, 0)

(1, 1)

; XOR only cares that they agree, not what value they agree on.

What does NAND with a single input tied to constant

1

compute, e.g.

A NAND 1

\overline{A \cdot 1} = \overline{A}

— feeding a constant

1

turns the NAND into a plain inverter of the other input.

What does NOR with one input held at constant

1

always produce?

\overline{A + 1} = \overline{1} = 0

— a constant

1

on any NOR input forces the output to

0

regardless of the other input.

For a chained XOR over zero bits (an empty group), what is the parity result?

0

— because

0

is the identity element of XOR (

A \oplus 0 = A

), combining no bits at all must return that identity, just as an empty sum is

0

; and zero

1

s is an even count, so parity is even.

If you tie both inputs of an XOR gate together (

A \oplus A

), what do you get?

Always

0

— a value is never different from itself, so XOR of any bit with itself is

0

(a handy "clear to zero" trick).

If you tie both inputs of an XNOR gate together (

A ⊙ A

), what do you get?

Always

1

— a value always matches itself, so XNOR of a bit with itself is constant

1

For inputs

(1, 1)

, which of NAND, NOR, XOR, XNOR output

1

Only XNOR outputs

1

(inputs agree); NAND

= 0

(all ones), NOR

= 0

1

is present), XOR

= 0

(no difference).

Connections

AND, OR, NOT gates — the basics every trap here reduces to
Boolean Algebra Laws — De Morgan settles most "spot the error" items
Sum of Products (SOP) — why XOR/XNOR have those exact expressions
Universal Gates — the universality traps in full
Half Adder and Full Adder — XOR as the sum bit
Parity Bits & Error Detection — the parity edge cases
Karnaugh Maps — visual home of these truth tables