XOR, NAND, NOR, XNOR gates: Exercises — Hardware deep dive

Notation reminder (everything you need, in plain words):

For each gate, state the single input combination (for 2 inputs $A, B$ ) that makes its output the "odd one out": (a) NAND outputs $0$ ; (b) NOR outputs $1$ ; (c) XOR outputs $0$ for two equal inputs — name both such rows.

Recall Solution L1-Q1

(a) NAND $= \overline{A \cdot B}$ is $0$ only when $A \cdot B = 1$ , i.e. $A = 1, B = 1$ . Every other row gives $1$ . (b) NOR $= \overline{A + B}$ is $1$ only when $A + B = 0$ , i.e. $A = 0, B = 0$ . (c) XOR is $0$ when inputs are equal: the rows $(0, 0)$ and $(1, 1)$ .

L1-Q2

Fill the output column of this XNOR truth table (output $= 1$ when inputs are the same):

A	B	$A ⊙ B$
0	0	?
0	1	?
1	0	?
1	1	?

Recall Solution L1-Q2

XNOR fires when both bits match:

A	B	$A ⊙ B$
0	0	1 (match)
0	1	0 (differ)
1	0	0 (differ)
1	1	1 (match)

Level 2 — Application

L2-Q1

Evaluate directly: (a) $\overline{1 \cdot 1}$ (b) $\overline{0 + 0}$ (c) $1 \oplus 1$ (d) $0 ⊙ 0$ .

Recall Solution L2-Q1

(a) $1 \cdot 1 = 1$ , then $\overline{1} = 0$ (NAND of two 1s — the only 0 case). (b) $0 + 0 = 0$ , then $\overline{0} = 1$ (NOR of two 0s — the only 1 case). (c) equal inputs → XOR $= 0$ . (d) equal inputs → XNOR $= 1$ .

L2-Q2

Build a NOT gate and an OR gate using only NAND gates. Show the Boolean simplification for each.

Recall Solution L2-Q2 — refer to the wiring figure

NOT from one NAND: tie both inputs to $A$ . $A ⊼ A = \overline{A \cdot A} = \overline{A} (since A \cdot A = A, idempotence)$ OR from three NANDs: invert each input with a NAND-as-NOT, then NAND the two inverses. $(\overline{A}) ⊼ (\overline{B}) = \overline{\overline{A} \cdot \overline{B}} = De Morgan A + B$ The final $\overline{\overline{A} \cdot \overline{B}}$ becomes $A + B$ because De Morgan turns "NOT(AND of NOTs)" into "OR". See Universal Gates.

L2-Q3

Compute $\overline{A} B + A \overline{B}$ for all four input rows and confirm it equals XOR.

Recall Solution L2-Q3

A	B	$\overline{A} B$	$A \overline{B}$	sum
0	0	$1 \cdot 0 = 0$	$0 \cdot 1 = 0$	0
0	1	$1 \cdot 1 = 1$	$0 \cdot 0 = 0$	1
1	0	$0 \cdot 0 = 0$	$1 \cdot 1 = 1$	1
1	1	$0 \cdot 0 = 0$	$1 \cdot 0 = 0$	0

Output column $0, 1, 1, 0$ = XOR. ✅ (This is the SOP form.)

Level 3 — Analysis

L3-Q1

On which input row(s) do OR and XOR disagree? Prove it by comparing their full columns.

Recall Solution L3-Q1

A	B	$A + B$	$A \oplus B$	agree?
0	0	0	0	✔
0	1	1	1	✔
1	0	1	1	✔
1	1	1	0	✘

They disagree on exactly one row: $(1, 1)$ . OR = "at least one $1$ "; XOR = "an odd number of $1$ s". Two $1$ s is even, so XOR drops to $0$ .

L3-Q2

Show algebraically that $\overline{A \oplus B} = A ⊙ B$ — i.e. inverting XOR gives XNOR. Start from $A \oplus B = \overline{A} B + A \overline{B}$ .

Recall Solution L3-Q2

Apply the bar and use De Morgan (from Boolean Algebra Laws) to split the OR into an AND: $\overline{A \oplus B} = \overline{\overline{A} B + A \overline{B}} = \overline{(\overline{A} B)} \cdot \overline{(A \overline{B})}$ Now De Morgan each factor: $= (A + \overline{B}) (\overline{A} + B)$ Expand ( $\overline{A} A = 0$ , $B \overline{B} = 0$ drop out): $= A \overline{A} + A B + \overline{B} \overline{A} + \overline{B} B = A B + \overline{A} \overline{B}$ That is exactly the XNOR SOP: $A B + \overline{A} \overline{B}$ . ✅

L3-Q3

Chain XOR across the bits $1, 1, 0, 1$ left to right. What does the final value tell you about the count of $1$ s?

Recall Solution L3-Q3

Fold left to right: $1 \oplus 1 = 0, 0 \oplus 0 = 0, 0 \oplus 1 = 1$ Final value $1$ → an odd number of $1$ s. (There are three $1$ s — odd. ✔) This is the parity idea in Parity Bits & Error Detection.

Level 4 — Synthesis

L4-Q1

Build XOR using only 4 NAND gates. Give the expression, then verify with $A = 1, B = 1$ and $A = 0, B = 1$ .

Recall Solution L4-Q1 — trace the 4-NAND network

A \oplus B = (A ⊼ (A ⊼ B)) ⊼ (B ⊼ (A ⊼ B))

Let

M = A ⊼ B

(the shared middle NAND).

Case $A = 1, B = 1$ (expect $0$ , inputs equal):

$M = \overline{1 \cdot 1} = 0$
Left $= 1 ⊼ 0 = \overline{0} = 1$
Right $= 1 ⊼ 0 = \overline{0} = 1$
Out $= 1 ⊼ 1 = \overline{1} = 0$ ✅

Case $A = 0, B = 1$ (expect $1$ , inputs differ):

$M = \overline{0 \cdot 1} = 1$
Left $= 0 ⊼ 1 = \overline{0} = 1$
Right $= 1 ⊼ 1 = \overline{1} = 0$
Out $= 1 ⊼ 0 = \overline{0} = 1$ ✅

L4-Q2

A half adder adds two bits $A, B$ producing a sum bit $S$ and carry bit $C$ . Express $S$ and $C$ with the gates on this page, then compute the outputs for all four inputs.

Recall Solution L4-Q2

Adding one-bit numbers: $1 + 1 = 1 0_{2}$ → sum digit $0$ , carry $1$ . The sum is $1$ when inputs differ (XOR); the carry is $1$ only when both are $1$ (AND): $S = A \oplus B, C = A \cdot B$

A	B	$S = A \oplus B$	$C = A \cdot B$	as number
0	0	0	0	$0$
0	1	1	0	$1$
1	0	1	0	$1$
1	1	0	1	$2 = 1 0_{2}$

See Half Adder and Full Adder.

Level 5 — Mastery

L5-Q1

Prove that NOR is universal by building NOT, OR, and AND from NOR only. (NOR: $A ↓ B = \overline{A + B}$ .)

Recall Solution L5-Q1

NOT: tie both inputs together. $A ↓ A = \overline{A + A} = \overline{A} (since A + A = A)$ OR: NOR then NOT (invert the NOR back). $\overline{\overline{A + B}} = A + B \Rightarrow OR = (A ↓ B) ↓ (A ↓ B)$ AND: invert each input first, then NOR. $(\overline{A}) ↓ (\overline{B}) = \overline{\overline{A} + \overline{B}} = De Morgan A \cdot B$ All three basics built → NOR is universal, just like NAND. See Universal Gates.

L5-Q2

Using a K-map intuition (or Boolean laws), simplify $F = \overline{A} \overline{B} + \overline{A} B + A B$ and identify the resulting gate.

Recall Solution L5-Q2

Group the first two terms (they share $\overline{A}$ ): $\overline{A} \overline{B} + \overline{A} B = \overline{A} (\overline{B} + B) = \overline{A} \cdot 1 = \overline{A}$ So $F = \overline{A} + A B$ . Apply the absorption-style law $\overline{A} + A B = \overline{A} + B$ (since $\overline{A} + A = 1$ lets $B$ pass): $F = \overline{A} + B$ This is $1$ except when $A = 1, B = 0$ — the truth table $1, 1, 0, 1$ . It is the implication gate ( $A \Rightarrow B$ ), equivalently NOT-A OR B.

A	B	$\overline{A} + B$
0	0	1
0	1	1
1	0	0
1	1	1

L5-Q3

Generalise the parity result: for $n$ bits, the XOR of all of them equals $1$ iff the number of $1$ s is odd. Prove the inductive step for one extra bit.

Recall Solution L5-Q3

Let $P_{n}$ = XOR of the first $n$ bits, and suppose $P_{n} = 1$ exactly when the count of $1$ s so far is odd (base case: one bit, $P_{1} = b_{1}$ , trivially true). Add bit $b_{n + 1}$ : $P_{n + 1} = P_{n} \oplus b_{n + 1}$ .

If $b_{n + 1} = 0$ : $P_{n + 1} = P_{n}$ — count unchanged, parity unchanged. ✔
If $b_{n + 1} = 1$ : $P_{n + 1} = \overline{P_{n}}$ — count increases by one, flipping odd↔even, and XOR-with-1 flips $P_{n}$ . ✔ In both cases $P_{n + 1}$ tracks the parity of the new count, so the claim holds for all $n$ by induction. This is why a single chained-XOR line is a parity bit generator.

Recall Final self-check (cover the answers)

Odd-one-out row for NAND? ::: $(1, 1)$ → output $0$ . XOR vs OR disagree where? ::: Only at $(1, 1)$ : OR $= 1$ , XOR $= 0$ . Half adder sum and carry? ::: $S = A \oplus B$ , $C = A \cdot B$ . NOT from one NOR? ::: $A ↓ A = \overline{A}$ . Chained XOR of $1, 1, 0, 1$ ? ::: $1$ (odd count of 1s).

Connections

XOR, NAND, NOR, XNOR gates — parent topic
Boolean Algebra Laws — De Morgan & absorption used throughout
AND, OR, NOT gates — the basics we rebuild
Sum of Products (SOP) — source of the XOR/XNOR expressions
Half Adder and Full Adder — L4-Q2
Parity Bits & Error Detection — L3-Q3, L5-Q3
Karnaugh Maps — L5-Q2 simplification
Universal Gates — L2-Q2, L5-Q1

Exercises — XOR, NAND, NOR, XNOR gates

Level 1 — Recognition

L1-Q1