Worked examples — Channel length and short-channel effects

This deep-dive drills the formulas from the parent note across every case class — long vs short channel, low vs high field, zero/degenerate inputs, limiting values, a real-world word problem, and an exam twist. Guess before you compute: forecasting sharpens intuition.

Everything here rests on the parent's four effects. If any symbol feels unfamiliar, re-read the parent's definitions first — here we only use them, exhaustively.

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The scenario matrix

Every problem this topic can throw at you falls into one of these cells. Each worked example below is tagged with the cell(s) it covers.

Cell	What it tests	Covered by
A. Long channel (baseline)	Formulas reduce to ideal; $\Delta V_T\to 0$	Ex 1
B. Short channel (roll-off)	$\Delta V_T$ grows as $1/L$	Ex 1, Ex 2
C. Low lateral field	$E\ll E_{crit}$: square law survives	Ex 3
D. High lateral field	$E\gg E_{crit}$: linear (velocity-sat) law	Ex 3
E. DIBL / leakage	Drain lowers barrier → $I_{off}$ up	Ex 4
F. Vertical-field mobility	High $V_{GS}$ crushes carriers → ${\mu }_{eff}\downarrow$	Ex 5
G. Zero / degenerate input	$V_{DS}=0$, $\eta =0$, $L\to \infty$ sanity	Ex 6
H. Limiting value (punch-through)	Depletion wedges merge; switch fails	Ex 7
I. Real-world word problem	Combine CLM + output resistance	Ex 8
J. Exam-style twist	Multi-effect current ratio	Ex 9

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Symbols used on this page (all from the parent)

Recall Quick symbol refresh

$L$ ::: channel length (source-to-drain distance under the gate) $x_j$ ::: junction depth (how deep source/drain diffusions go) $x_{dm}$ ::: vertical gate-depletion depth into the bulk $x_{dS},x_{dD}$ ::: lateral source/drain depletion reaching sideways into the channel $C_{ox}={\epsilon }_{ox}/t_{ox}$ ::: oxide capacitance per area (F/m${}^2$) $Q_B$ ::: bulk depletion charge the gate must support ${\varphi }_F$ ::: Fermi potential — how far the bulk's Fermi level sits from mid-gap (measures doping strength, in volts); $2{\varphi }_F$ is the surface potential needed to fully invert the channel $E=V_{DS}/L$ ::: lateral field along the channel $E_{crit}$ ::: field at which velocity saturates $v_{sat}$ ::: saturated drift velocity, the carrier speed limit; $v_{sat}=\mu E_{crit}$ $W$ ::: transistor width (how wide the channel is, perpendicular to current flow); more width = more parallel current $V_{ov}=V_{GS}-V_T$ ::: overdrive voltage — how far the gate is driven above threshold; the true "on-ness" knob $\eta$ ::: DIBL coefficient (mV of $V_T$ drop per V of $V_{DS}$) $S$ ::: subthreshold swing (mV per decade of current) $\theta$ ::: vertical-field mobility-degradation coefficient (V${}^{-1}$) $\lambda$ ::: channel-length-modulation coefficient (V${}^{-1}$)

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Example 1 — Long vs short channel roll-off (Cells A, B)

Forecast: The corner triangles are the same absolute size in both. So the fraction they steal should scale like $1/L$ — expect roughly a $\times 20$ jump going from 1 µm to 50 nm.

1. Compute the square-root piece (shared). $\sqrt{1+2\cdot 40/30}-1=\sqrt{1+2.667}-1=\sqrt{3.667}-1=1.915-1=0.915$. Why this step? This term encodes how far the junction wedges reach relative to $x_j$; it does not depend on $L$, so we compute it once.

2. Long device. $g=\frac{30}{1000}\times 0.915=0.0275$. Why this step? $x_j/L$ is tiny (0.03) — the corners are a negligible slice of a 1 µm channel. This is Cell A: the gate owns ~97% of the charge, so it behaves ideally.

3. Short device. $g=\frac{30}{50}\times 0.915=0.549$. Why this step? Now $x_j/L=0.6$ — the same corners eat over half the channel. This is Cell B: massive roll-off.

4. Ratio. $0.549/0.0275=20.0$. Why this step? Confirms the roll-off is $\approx 20\times$ worse, exactly the $1000/50$ length ratio predicted.

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Example 2 — Turning $g$ into millivolts (Cell B)

Forecast: Roll-off should be a chunk of $V_T$ — tens to a couple hundred mV. If we get volts, we blundered a unit.

1. Oxide capacitance. $C_{ox}={\epsilon }_{ox}/t_{ox}=3.45\times 10^{-11}/4\times 10^{-9}=8.625\times 10^{-3}{\text{F/m}}^2$. Why this step? $\Delta V_T=-\frac{Q_B}{C_{ox}}g$ needs $C_{ox}$ to turn charge into voltage.

2. Bulk charge. $Q_B=\sqrt{2q{\epsilon }_{si}{N}_A(2{\varphi }_F)}=\sqrt{2(1.6\times 10^{-19})(1.04\times 10^{-10})(10^{23})(0.84)}$. Inside: $2\times 1.6\times 10^{-19}=3.2\times 10^{-19}$; $\times 1.04\times 10^{-10}=3.33\times 10^{-29}$; $\times 10^{23}=3.33\times 10^{-6}$; $\times 0.84=2.79\times 10^{-6}$. So $Q_B=\sqrt{2.79\times 10^{-6}}=1.67\times 10^{-3}{\text{C/m}}^2$. Why this step? This is the depletion charge the gate must support in a long device — the thing the wedges steal.

3. Roll-off voltage. $\Delta V_T=-\frac{1.67\times 10^{-3}}{8.625\times 10^{-3}}\times 0.549=-0.194\times 0.549=-0.106\text{V}$. Why this step? Multiply the charge ratio by the geometric fraction; the minus sign says $V_T$ drops.

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Example 3 — Which current law? Low vs high lateral field (Cells C, D)

Forecast: Same voltage, but Y's field is ~20× bigger (20× shorter $L$). X should stay linear-mobility (square law); Y should be velocity-saturated (linear law).

1. Field in X. $E=0.9/(1\times 10^{-6}\text{m})=9\times 10^5\text{V/m}=9\text{kV/cm}$. Why this step? $E=V_{DS}/L$ is the lateral field driving carriers; comparing it to $E_{crit}$ decides the regime.

2. Compare X. $9\text{kV/cm}<40\text{kV/cm}$ → Cell C: below the speed limit, $v=\mu E$, so $I_{D,sat}\propto (V_{GS}-V_T{)}^2$ (square law survives).

3. Field in Y. $E=0.9/(45\times 10^{-9})=2\times 10^7\text{V/m}=200\text{kV/cm}$. Why this step? Same $V_{DS}$ crammed into 45 nm.

4. Compare Y. $200\text{kV/cm}\gg 40\text{kV/cm}$ → Cell D: carriers hit $v_{sat}$ (the saturated drift velocity — the carrier speed limit), so $I_{D,sat}\approx W{C}_{ox}{v}_{sat}(V_{GS}-V_T{)}^1$ (linear). Here $W$ is the transistor width: a wider channel just puts more identical current paths in parallel, so drive scales with $W$.

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Example 4 — DIBL leakage explosion (Cell E)

Forecast: A 100 mV $V_T$ drop, with 90 mV per 10×, is a bit more than one decade — expect roughly a $\times 10$–$15$ leakage blow-up.

1. Effective $V_T$ drop. $\Delta V_T=\eta V_{DS}=0.100\times 1=0.100\text{V}=100\text{mV}$. Why this step? DIBL says $V_T(V_{DS})=V_T(0)-\eta V_{DS}$; the drain lowers the barrier as if you nudged the gate.

2. Convert to decades of current. decades $=\Delta V_T/S=100/90=1.11$. Why this step? $S$ is how many mV of gate drive move the current one decade — so $\Delta V_T/S$ is how many decades of leakage we just unlocked.

3. Leakage factor. $10^{1.11}=12.9\approx 13\times$. Why this step? Each decade = ×10; 1.11 decades = ×12.9.

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Example 5 — Vertical-field mobility hit (Cell F)

Forecast: More overdrive presses carriers harder into the rough interface, so ${\mu }_{eff}$ should fall as $V_{ov}$ rises. The 1 V case should be noticeably slower than 0.5 V.

1. At $V_{ov}=0.5$. ${\mu }_{eff}/{\mu }_0=\frac{1}{1+0.5\times 0.5}=\frac{1}{1.25}=0.800$. Why this step? ${\mu }_{eff}={\mu }_0/(1+\theta V_{ov})$; here $V_{ov}=V_{GS}-V_T$ is the overdrive — how far the gate is above threshold — and a higher denominator means more degradation.

2. At $V_{ov}=1.0$. ${\mu }_{eff}/{\mu }_0=\frac{1}{1+0.5\times 1}=\frac{1}{1.5}=0.667$. Why this step? Doubling overdrive doesn't double degradation (it's not linear) — but it clearly worsens it.

3. Ratio. $0.667/0.800=0.833$. Why this step? Going from 0.5 V to 1 V overdrive costs another ~17% of mobility on top of the velocity-saturation ceiling — the drive current rises sublinearly with $V_{GS}$.

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Example 6 — Degenerate / zero inputs (Cell G)

Forecast: Every short-channel effect must vanish when you remove its cause. If any survives, the formula is wrong.

1. (a) Zero drain bias. $V_T(V_{DS}=0)=V_T(0)-\eta \cdot 0=V_T(0)$. Why this step? With no drain field there is nothing to lower the barrier — DIBL must disappear. It does: $\Delta =0$. ✓

2. (b) Zero DIBL coefficient. $V_T(V_{DS})=V_T(0)-0\cdot V_{DS}=V_T(0)$ for all $V_{DS}$. Why this step? $\eta =0$ describes an ideal long device the drain can't influence — threshold is flat vs $V_{DS}$. ✓

3. (c) Infinite length. $\Delta V_T=-\frac{Q_B}{C_{ox}}\cdot \frac{x_j}{L}(\cdots )\stackrel{L\to \infty }{\to }0$. Why this step? Fixed corner triangles are an infinitesimal fraction of an infinite channel — roll-off →0, recovering $V_{T0}$. ✓

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Example 7 — Punch-through limit (Cell H)

Forecast: We need $x_{dD}=60-20=40$ nm. Since $x_{dD}=25\text{nm}$ at 1 V and grows as $\sqrt{V}$, we need $V_{DS}$ a bit above 2 V.

1. Required drain-side width. $x_{dD}=L-x_{dS}=60-20=40\text{nm}$. Why this step? Punch-through is exactly the $L\lesssim x_{dS}+x_{dD}$ condition at equality — the two triangular wedges touch.

2. Solve for the dimensionless bias ratio. Set $40=25\sqrt{V_{DS}/V_0}$, so $\sqrt{V_{DS}/V_0}=40/25=1.6$, giving $V_{DS}/V_0=1.6^2=2.56$. Why this step? Keeping $V_{DS}/V_0$ dimensionless makes the square-root law unit-clean; only the ratio to the reference bias appears.

3. Restore the voltage. $V_{DS}=2.56\times V_0=2.56\times 1\text{V}=2.56\text{V}$. Why this step? Multiply the dimensionless ratio by $V_0=1\text{V}$; above this bias the gate can no longer block the sub-surface path.

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Example 8 — Real-world word problem: output resistance from CLM (Cell I)

Forecast: CLM makes $I_D$ creep up ~10% by 1 V; a finite $r_o$ in the tens of k$\Omega$ means an imperfect current source.

1. Actual current. $I_D=I_{D,sat}(1+\lambda V_{DS})=200\mu \text{A}\times (1+0.1\times 1)=200\times 1.1=220\mu \text{A}$. Why this step? CLM: as $V_{DS}$ rises the pinch-off point moves back, shortening the effective channel, so $I_D$ keeps climbing.

2. Output resistance. $r_o=\frac{1}{\lambda I_{D,sat}}=\frac{1}{0.1\times 200\times 10^{-6}}=\frac{1}{2\times 10^{-5}}=50\text{k}\Omega$. Why this step? $r_o$ is the slope's inverse — how flat the $I_D$–$V_{DS}$ curve is. We use $I_{D,sat}$ (the current at the saturation edge, $V_{DS}$-independent) not the actual $I_D$, because $r_o$ is defined as the inverse slope of the line $I_D=I_{D,sat}(1+\lambda V_{DS})$; that slope is $\lambda I_{D,sat}$, a constant set by the baseline current. Using the biased $I_D$ would double-count the CLM correction we are trying to measure.

3. Judgement. 50 k$\Omega$ is finite → the mirror leaks current with $V_{DS}$: $I_D$ drifts ~10% per volt, so a not-ideal current source. Short channels (large $\lambda \propto 1/L$) make analog mirrors worse — designers restore accuracy by using longer $L$ or a cascode to raise $r_o$. Why this step? Connects the number back to the design consequence and directly answers the posed question.

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Example 9 — Exam twist: stack all the effects (Cell J)

Forecast: Two multiplicative penalties, each roughly a third off — combined they should chop the ideal current well below half.

1. Apply velocity saturation. $I_1=0.55\times 500=275\mu \text{A}$. Why this step? Velocity saturation replaces the square law with a linear law, a fixed drive-fraction here (the carriers are already pinned at $v_{sat}$).

2. Apply mobility degradation. $I_{on}=0.667\times 275=183.4\mu \text{A}$. Why this step? The two mechanisms are independent physical slowdowns (lateral speed limit × vertical surface scattering), so they multiply.

3. Total loss. fraction retained $=0.55\times 0.667=0.367$, so loss $=1-0.367=0.633=63.3\%$. Why this step? Shows why the naive $\propto (V_{GS}-V_T{)}^2$ estimate wildly overpredicts real scaled-transistor current — this is the classic exam "gotcha" (stack the effects, don't pick one).

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Recall Self-test (reveal after guessing)

Which cell fires when $E\ll E_{crit}$? ::: Cell C — square law survives. Punch-through is which limiting condition pushed to equality? ::: $x_{dS}+x_{dD}=L$ (wedges merge). Removing $\eta$ should do what to $V_T(V_{DS})$? ::: Make it flat (no DIBL) — Cell G sanity. Why do velocity saturation and vertical-field mobility multiply? ::: They are independent physical slowdowns (lateral speed limit × vertical surface scattering). Why use $I_{D,sat}$ (not the biased $I_D$) in $r_o=1/(\lambda I_{D,sat})$? ::: $r_o$ is the inverse of the constant slope $\lambda I_{D,sat}$; the baseline current sets that slope.

Related: MOSFET operation and regions · Velocity saturation and carrier transport · Surface scattering and effective mobility · Drain-Induced Barrier Lowering (DIBL) · Subthreshold conduction and leakage · Depletion region physics of pn junctions · Scaling theory (Dennard scaling)