(a) DIBL — the change is driven by VDS, not L. The drain lowers the source barrier.
(b) Threshold roll-off (VT lowering) — a length dependence at fixed VDS; source/drain
wedges share the bulk charge.
(c) Channel-length modulation (CLM) — the pinch-off point moves toward the source as VDS
rises, so effective L shrinks.
(d) Velocity saturation — carriers hit vsat, so ID,sat∝(VGS−VT)1.
Lateral widths xdS,xdD (source/drain depletion pushing sideways into the channel)
set the onset: short-channel when L≲xdS+xdD.
Vertical depth xdm (gate depletion reaching down into the bulk) sets the roll-off
geometry through the trapezoid.
Directions differ: one is horizontal along the channel, the other is vertical into the substrate.
A parallel-plate capacitor stores charge in proportion to its plate area and inversely to the gap;
here the "plates" are the gate and the channel, and tox is the gap. So capacitance per unit
area is permittivity over gap:
Cox=toxεox=4×10−93.45×10−11=8.625×10−3F/m2.Why this quantity? It converts a sheet charge (C/m²) into a voltage (V) — every
threshold term Q/Cox is exactly that conversion. A thinner oxide (smaller tox) gives a
bigger Cox and a stronger grip of the gate on the channel.
QB=2(1.602×10−19)(1.04×10−10)(1023)(0.84).
Inside: 2×1.602×10−19=3.204×10−19; times 1.04×10−10=3.332×10−29;
times 1023=3.332×10−6; times 0.84=2.799×10−6.
QB=2.799×10−6=1.673×10−3C/m2.
Then
ΔVT=−8.625×10−31.673×10−3(0.5489)=−(0.1940)(0.5489)=−0.1065V.
So about −107mV of roll-off at 50 nm — huge. At 1 µm the same computation with g=0.02745
gives only ≈−5.3mV.
(a) E=45×10−9m0.9V=2×107V/m=200kV/cm.
(b) E=200kV/cm ≫Ecrit=40kV/cm (factor 5). Carriers are velocity saturated, so
ID,sat≈WCoxvsat(VGS−VT)∝(VGS−VT)1.Why compare to Ecrit?Ecrit is the field where drift velocity is halfway to vsat;
above it the velocity flattens, so the current stops caring about extra field and the square law
dies.
Barrier drop =η⋅ΔVDS=100mV ×1=100mV effective VT reduction.
Sub-threshold current changes by a decade for every S=90mV, so
Ioff(0)Ioff(1V)=10ΔVT/S=10100/90=101.111=12.9×.
A single volt of drain swing multiplies leakage by ~13.
At 1 V: μeff/μ0=1+0.5×11=1.51=0.6667.
At 1.5 V: μeff/μ0=1+0.5×1.51=1.751=0.5714.
Pushing harder on the gate reduces mobility — the extra vertical field crushes carriers into the
rough Si–SiO₂ interface, adding surface-roughness scattering.
Base velocity-saturated current:
ID,sat=WCoxvsat(VGS−VT)=(10−6)(8.625×10−3)(105)(0.6).
Multiply: (10−6)(8.625×10−3)=8.625×10−9; ×105=8.625×10−4;
×0.6=5.175×10−4A=0.5175mA.
Mobility factor at 0.6 V overdrive: 1/(1+0.5×0.6)=1/1.3=0.7692.
Corrected: 0.5175mA×0.7692=0.398mA.Why multiply? The mobility term degrades the effective drive; the velocity ceiling sets the base
current, then the surface-scattering factor scales it down.
Drain (VD=2.2V): xdD=1.298×10−14×2.2=2.856×10−14=1.690×10−7m=169.0nm.
Sum =95.3+169.0=264.3nm ≫50nm. Punch-through: the wedges overlap the whole channel.(These idealized widths ignore 2-D screening and the gate's control, but the comparison to L
correctly flags catastrophic overlap.)
Thin the gate oxide (tox↓) → Cox↑ → stronger gate control of the
channel charge, restoring the gate's authority over roll-off and DIBL. (This is the
Dennard prescription.)
Raise channel doping NA (or use halo/pocket implants) → depletion widths
xd∝1/NA shrink → the lateral wedges that cause charge-sharing and DIBL get
smaller, and punch-through is pushed to higher VDS. Cost: higher VT and more
body effect.
Reduce junction depth xj (shallow source/drain, extensions) → the roll-off factor
∝xj/L falls directly, so the triangular corners consume less of the channel.
Each attacks a different geometric term rather than one blanket fix.
Related: Velocity saturation and carrier transport · Drain-Induced Barrier Lowering (DIBL) ·
Subthreshold conduction and leakage · Surface scattering and effective mobility ·
Depletion region physics of pn junctions · MOSFET operation and regions.
