Exercises — DMA — memory-to-memory, peripheral-to-memory without CPU

Answer: (b) ADC → RAM buffer (peripheral-to-memory).

Why. The ADC's data register is a single fixed hardware address — new samples appear at the same spot each time. So we read that one address repeatedly (${\Delta }_S=0$) and scatter the results into successive RAM slots (${\Delta }_D=w$).

• (a) Mem-to-mem: both increment (${\Delta }_S={\Delta }_D=w$).
• (c) Mem-to-periph: the destination (DAC register) is fixed (${\Delta }_D=0$), source increments.

Rule of thumb: the peripheral side is always the fixed address. See Memory-Mapped IO for why a peripheral register lives at one address.

• Item count $=N$
• Bus clock $=f$ (Hz)
• Bytes per item $=w$
• Cycles per beat $=c$

Memory aid: only $w$ and $c$ set the rate ($wf/c$); $N$ only sets how long it runs.

False. DMA is asynchronous — dma_start() only launches the mover. The bytes arrive over the next $t_{\text{DMA}}$ seconds. You must wait for the transfer-complete flag or interrupt (see Interrupts and ISRs) before reading. Reading early gives stale or partial data.

Time: plug into $t=Nc/f$. $t=\frac{512\times 1}{40\times 10^6}=1.28\times 10^{-5}\text{ s}=12.8\mu s$ Why this step: each beat is 1 cycle, we have 512 beats, and $f$ tells us cycles per second — dividing gives seconds.

Throughput: $\text{Throughput}=\frac{wf}{c}=\frac{1\times 40\times 10^6}{1}=40\text{ MB/s}.$ (Sanity check: $B=512$ bytes, $B/t=512/12.8\mu s=40$ MB/s. ✓)

Bytes: $B=Nw=300\times 4=1200$ bytes. Time: $t=Nc/f=300/(60\times 10^6)=5\times 10^{-6}=5\mu s$. Address increments: both walk forward, ${\Delta }_S={\Delta }_D=4$ bytes per beat (this is what makes it a copy — see memcpy and Block Copy).

• $w=1\Rightarrow N=8192$: $t_1=8192/(50\times 10^6)=163.84\mu s$.
• $w=4\Rightarrow N=2048$: $t_4=2048/(50\times 10^6)=40.96\mu s$.
• Ratio $t_1/t_4=4$. The $w=4$ transfer is 4× faster.

Why: same total bytes, but wider beats mean fewer beats, and each beat costs the same $c$ cycles. Fewer cycles → less time. Always use the widest width your source/destination alignment permits.

Two rates compete:

• How fast DMA could move a beat: $t_{\text{beat}}=c/f=1/(48\times 10^6)\approx 20.8\text{ns}$.
• How often data arrives: one request every $2000\text{ns}$.

Since $20.8\text{ns}\ll 2000\text{ns}$, the DMA finishes each beat in a blink and then waits for the next request. The ADC is the bottleneck — the transfer is rate-matched to the peripheral.

Effective throughput = bytes per sample ÷ sample period: $\frac{w}{2\mu s}=\frac{2\text{ bytes}}{2\times 10^{-6}\text{ s}}=1\times 10^6=1\text{ MB/s}$ Not the raw $wf/c=96$ MB/s! The formula $wf/c$ is the DMA's ceiling; the real rate is throttled by how often the peripheral has data. See ADC and DAC.

Burst mode: DMA owns the bus for the entire $40.96\mu s$. Every CPU memory access in that window stalls until DMA finishes. Worst case, the CPU is blocked for nearly the full $\approx 41\mu s$ (all its memory accesses queue up).

Cycle-stealing: DMA takes the bus for one beat ($t_{\text{beat}}=20\text{ns}$) then releases it. A CPU access arriving during a beat waits at most one beat $=20\text{ns}$. Over the whole block the CPU loses only $\approx 2048\times 20\text{ns}=40.96\mu s$ of bus occupancy spread out — but any single CPU access is delayed by at most $20$ ns, so the CPU keeps running, just slightly slowed.

The trade-off: burst = highest DMA throughput, worst CPU latency. Cycle-stealing = bounded CPU latency, slightly lower DMA throughput (arbitration overhead between beats). This is exactly the Bus Arbitration decision.

Cycles saved: ${\Delta }_{\text{CPU}}=Nk=4000\times 4=16000$ cycles. Time freed: ${\Delta }_{\text{CPU}}/f=16000/(80\times 10^6)=2\times 10^{-4}\text{ s}=200\mu s$.

Why this matters: the CPU spends only $O(1)$ cycles (setup + one interrupt handler) instead of $O(N)$ babysitting the copy. Those $200\mu s$ go to real computation while DMA plumbs the bytes.

Scheme: double buffering (ping-pong). Split one buffer into two halves. DMA streams half A to the DAC while the CPU fills half B; when DMA finishes A it fires a half-transfer / transfer-complete interrupt and switches to B while the CPU refills A. No gaps. This is Circular and Double Buffering.

Refill deadline. One half = 512 samples, each played every $1/48000$ s: $t_{\text{half}}=\frac{512}{48000}\approx 1.067\times 10^{-2}\text{ s}=10.67\text{ms}$ So the CPU has ~10.67 ms to refill one half before DMA drains the other. Miss this deadline → audible glitch. This is the essence of deterministic real-time DMA. (Mem-to-periph: ${\Delta }_S=w=2$, ${\Delta }_D=0$ at the DAC register.)

Required: after the CPU writes new samples, clean (flush) the cache for that buffer region before enabling the DMA read. Cleaning pushes the cached values down into actual RAM, which is where DMA reads from.

If skipped: the fresh samples may still sit only in the CPU's write-back cache, while RAM holds stale bytes. DMA reads RAM → plays old/garbage audio. This is the classic Cache Coherency bug.

Mirror case (periph→mem input): before the CPU reads a DMA-filled buffer, invalidate the cache for that region so the CPU fetches fresh RAM instead of a stale cached copy.

SCAM setup:

• Source $=$ ADC data register, fixed (${\Delta }_S=0$).
• Count $N=1000$ (one block).
• Address mode: destination increments by $w=2$ (${\Delta }_D=2$); source fixed.
• Mode/trigger: hardware-triggered by the ADC "conversion ready" DMA request — one beat per sample, naturally rate-matched. Use circular / double buffering so capture never stops: DMA fires a half-transfer interrupt at 500 samples and a full-transfer interrupt at 1000, ping-ponging halves.

Timing check — does the CPU keep up?

• Time to fill one 1000-sample block at 100 kHz: $t_{\text{fill}}=\frac{1000}{100000}=1\times 10^{-2}\text{ s}=10\text{ms}$
• Time for the CPU to process one block: $t_{\text{proc}}=\frac{50000}{48\times 10^6}\approx 1.042\times 10^{-3}\text{ s}\approx 1.04\text{ms}$
• Since $t_{\text{proc}}=1.04\text{ms}\ll t_{\text{fill}}=10\text{ms}$, the CPU finishes with ~8.96 ms to spare per block. ✓ The system is comfortably real-time.

CPU utilisation for processing $=t_{\text{proc}}/t_{\text{fill}}=1.042/10\approx 10.4\%$ — the other ~90% is free for other tasks, exactly the DMA parallelism win.

New fill time at 800 kHz: $t_{\text{fill}}=\frac{1000}{800000}=1.25\times 10^{-3}\text{ s}=1.25\text{ms}$ Processing still needs $t_{\text{proc}}\approx 1.04\text{ms}$. Now $t_{\text{proc}}/t_{\text{fill}}=1.042/1.25\approx 83.4\%$ — it still fits, but barely: only ~0.21 ms of slack. Any interrupt jitter, cache miss, or added work can blow the deadline.

Two fixes:

1. Bigger blocks — process 4000 samples per block. Fill time $=4000/800000=5\text{ms}$; processing $\approx 4\times 1.04=4.17\text{ms}$, still fits, but the fixed per-block overhead (interrupt entry, cache invalidate) is amortised over more samples, lowering effective per-sample cost.
2. Optimise processing — cut cycles/block (better algorithm, use of hardware accelerators) so $t_{\text{proc}}$ drops well below $t_{\text{fill}}$, restoring margin.

Verify the CPU never touches the ADC register itself — DMA does all capture; the CPU only wakes on the transfer-complete interrupt. Also invalidate the cache on the DMA input buffer before processing (Cache Coherency).

$t=Nc/f$ :::: transfer time from beats, cycles/beat, clock $\text{Throughput}=wf/c$ :::: rate ceiling; $N$ cancels Peripheral side address increment :::: always $\Delta =0$ (fixed register) Real bottleneck of a periph transfer :::: the peripheral's request rate, not $wf/c$ Before CPU reads DMA input (with cache) :::: invalidate cache Before DMA reads CPU output (with cache) :::: clean/flush cache