DMA — memory-to-memory, peripheral-to-memory without CPU: Exercises

5.5.8 · D4 · Coding › Embedded Systems & Real-Time Software › DMA — memory-to-memory, peripheral-to-memory without CPU

Shuru karne se pehle, sirf teen formulas jo tumhe chahiye, simple shabdon mein restate karte hain, taaki kuch bhi bina samjhaye use na ho.

Level 1 — Recognition

Exercise 1.1

Inn teen transfers mein se kaun sa source address fixed rakhta hai (har beat mein use increment nahi karta)? (a) Mem-to-mem memcpy (b) ADC → RAM buffer (c) RAM buffer → DAC

Recall Solution 1.1

Answer: (b) ADC → RAM buffer (peripheral-to-memory).

Kyun. ADC ka data register ek single fixed hardware address hota hai — naye samples har baar usi jagah appear hote hain. Toh hum usi ek address ko baar baar read karte hain ( $Δ_{S} = 0$ ) aur results ko RAM ke successive slots mein scatter karte hain ( $Δ_{D} = w$ ).

(a) Mem-to-mem: dono increment hote hain ( $Δ_{S} = Δ_{D} = w$ ).
(c) Mem-to-periph: destination (DAC register) fixed hota hai ( $Δ_{D} = 0$ ), source increment karta hai.

Rule of thumb: peripheral side hamesha fixed address hoti hai. Dekho Memory-Mapped IO kyun ek peripheral register ek address par rehta hai.

Exercise 1.2

Har quantity ko uske symbol se match karo: item count, bus clock, bytes per item, cycles per beat.

Recall Solution 1.2

Item count $= N$
Bus clock $= f$ (Hz)
Bytes per item $= w$
Cycles per beat $= c$

Memory aid: sirf $w$ aur $c$ rate set karte hain ( $w f / c$ ); $N$ sirf yeh set karta hai ki kitna time chalega.

Exercise 1.3

Sach ya jhooth: "Jaise hi main dma_start() call karta hoon, destination buffer mein saara data aa jaata hai."

Recall Solution 1.3

Jhooth. DMA asynchronous hota hai — dma_start() sirf mover ko launch karta hai. Bytes agli $t_{DMA}$ seconds mein aate hain. Padhne se pehle tumhe transfer-complete flag ya interrupt ka wait karna padega (dekho Interrupts and ISRs). Jaldi padhne par stale ya partial data milega.

Level 2 — Application

Exercise 2.1

Ek UART bytes ko RAM mein log karta hai (periph-to-mem), $w = 1$ , $N = 512$ , bus $f = 40$ MHz, $c = 1$ . $t_{DMA}$ aur throughput nikalo.

Recall Solution 2.1

Time: $t = N c / f$ mein plug karo. $t = \frac{512 \times 1}{40 \times 1 0 ^{6}} = 1.28 \times 1 0^{- 5} s = 12.8 μ s$ Yeh step kyun: har beat 1 cycle hai, hamare paas 512 beats hain, aur $f$ batata hai cycles per second — divide karne par seconds milte hain.

Throughput: $Throughput = \frac{w f}{c} = \frac{1 \times 40 \times 1 0 ^{6}}{1} = 40 MB/s .$ (Sanity check: $B = 512$ bytes, $B / t = 512/12.8 μ s = 40$ MB/s. ✓)

Exercise 2.2

300-word array ka mem-to-mem copy, $w = 4$ , $f = 60$ MHz, $c = 1$ . Bytes moved $B$ aur time $t$ nikalo.

Recall Solution 2.2

Bytes: $B = N w = 300 \times 4 = 1200$ bytes. Time: $t = N c / f = 300/ (60 \times 1 0^{6}) = 5 \times 1 0^{- 6} = 5 μ s$ . Address increments: dono aage badhte hain, $Δ_{S} = Δ_{D} = 4$ bytes per beat (yahi ise copy banata hai — dekho memcpy and Block Copy).

Exercise 2.3

Tumhe exactly 8192 bytes move karni hain. $w = 1$ vs $w = 4$ ko $f = 50$ MHz, $c = 1$ par compare karo. Kaun sa faster hai aur kitna?

Recall Solution 2.3

$w = 1 \Rightarrow N = 8192$ : $t_{1} = 8192/ (50 \times 1 0^{6}) = 163.84 μ s$ .
$w = 4 \Rightarrow N = 2048$ : $t_{4} = 2048/ (50 \times 1 0^{6}) = 40.96 μ s$ .
Ratio $t_{1} / t_{4} = 4$ . $w = 4$ transfer 4× faster hai.

Kyun: same total bytes, lekin wider beats matlab kam beats, aur har beat ko same $c$ cycles lagti hain. Kam cycles → kam time. Hamesha woh widest width use karo jo tumhara source/destination alignment allow kare.

Level 3 — Analysis

Exercise 3.1

Ek ADC har $2 μ s$ mein ek DMA request fire karta hai (ek sample per request, hardware-triggered). Har beat khud $c = 1$ cycle leti hai $f = 48$ MHz par. Kya DMA bottleneck hai, ya ADC? Effective throughput kya hai, $w = 2$ ?

Recall Solution 3.1

Do rates compete karte hain:

DMA ek beat kitni tez move kar sakta hai: $t_{beat} = c / f = 1/ (48 \times 1 0^{6}) \approx 20.8 ns$ .
Data kitni baar aata hai: har $2000 ns$ mein ek request.

Kyunki $20.8 ns ≪ 2000 ns$ , DMA har beat ek pal mein khatam kar leta hai aur phir agli request ka wait karta hai. ADC bottleneck hai — transfer peripheral ke rate se match hota hai.

Effective throughput = bytes per sample ÷ sample period: $\frac{w}{2 μ s} = \frac{2 bytes}{2 \times 1 0 ^{- 6} s} = 1 \times 1 0^{6} = 1 MB/s$ Raw $w f / c = 96$ MB/s nahi! Formula $w f / c$ DMA ki ceiling hai; asli rate is baat se throttle hoti hai ki peripheral kitni baar data lata hai. Dekho ADC and DAC.

Exercise 3.2

Burst mode mein DMA poore 2048-beat block ke liye bus hold karta hai; cycle-stealing mode mein woh ek beat leta hai, release karta hai, repeat karta hai. Block $t_{block} = 2048/ (50 \times 1 0^{6}) = 40.96 μ s$ leta hai ( $c = 1$ ). Is window mein CPU ko average har $200$ ns mein ek memory access chahiye. Burst mode vs cycle-stealing mein CPU roughly kitna stall hota hai?

Recall Solution 3.2

Burst mode: DMA poore $40.96 μ s$ ke liye bus own karta hai. Us window mein har CPU memory access tab tak stall hoti hai jab tak DMA khatam na ho. Worst case, CPU almost poore $\approx 41 μ s$ ke liye block hota hai (saari memory accesses queue ho jaati hain).

Cycle-stealing: DMA bus ek beat ( $t_{beat} = 20 ns$ ) ke liye leta hai phir release kar deta hai. Ek beat ke dauran aane wali CPU access zyada se zyada ek beat $= 20 ns$ wait karti hai. Poore block mein CPU sirf $\approx 2048 \times 20 ns = 40.96 μ s$ bus occupancy khoata hai spread out hoke — lekin koi bhi single CPU access zyada se zyada $20$ ns delay hoti hai, toh CPU chalti rehti hai, bas thodi slow.

Trade-off: burst = highest DMA throughput, worst CPU latency. Cycle-stealing = bounded CPU latency, thoda kam DMA throughput (beats ke beech arbitration overhead). Yeh exactly Bus Arbitration ka decision hai.

Exercise 3.3

Ek CPU copy loop mein $k = 4$ cycles/word lagti hain. Tumne $N = 4000$ words DMA-copy kiye. CPU kitne cycles bachata hai, aur ( $f = 80$ MHz par) CPU ka kitna time free hota hai?

Recall Solution 3.3

Cycles saved: $Δ_{CPU} = N k = 4000 \times 4 = 16000$ cycles. Time freed: $Δ_{CPU} / f = 16000/ (80 \times 1 0^{6}) = 2 \times 1 0^{- 4} s = 200 μ s$ .

Yeh kyun matter karta hai: CPU sirf $O (1)$ cycles (setup + ek interrupt handler) spend karta hai, na ki $O (N)$ cycles copy ko babysit karne mein. Woh $200 μ s$ asli computation mein jaate hain jabki DMA bytes plumb karta hai.

Level 4 — Synthesis

Exercise 4.1

Tum audio 48 kHz sample rate par, 2 bytes/sample, DAC ko stream kar rahe ho, aur CPU ke buffer refill karte waqt koi gap afford nahi kar sakte. Buffer scheme design karo aur compute karo ki agar har half mein 512 samples hain toh tumhare paas per half-buffer kitna time hai.

Recall Solution 4.1

Scheme: double buffering (ping-pong). Ek buffer ko do halves mein split karo. DMA half A ko DAC mein stream karta hai jabki CPU half B fill karta hai; jab DMA A khatam kare tab ek half-transfer / transfer-complete interrupt fire hoti hai aur B par switch ho jaata hai jabki CPU A refill karta hai. Koi gap nahi. Yeh Circular and Double Buffering hai.

Refill deadline. Ek half = 512 samples, har ek $1/48000$ s mein play hota hai: $t_{half} = \frac{512}{48000} \approx 1.067 \times 1 0^{- 2} s = 10.67 ms$ Toh CPU ke paas ~10.67 ms hai ek half refill karne ke liye, DMA doosra drain karne se pehle. Yeh deadline miss karo → audible glitch. Yeh deterministic real-time DMA ka essence hai. (Mem-to-periph: $Δ_{S} = w = 2$ , $Δ_{D} = 0$ DAC register par.)

Exercise 4.2

Same DAC stream, lekin SoC mein data cache hai. CPU RAM mein naye samples compute karta hai, phir DMA unhe read karta hai. Kaun sa cache operation required hai aur kab, aur skip karne par kya hota hai?

Recall Solution 4.2

Required: CPU ke naye samples likhne ke baad, DMA read enable karne se pehle us buffer region ke liye cache clean (flush) karo. Cleaning cached values ko actual RAM mein push karta hai, jahan se DMA read karta hai.

Skip karne par: fresh samples CPU ke write-back cache mein hi baith sakte hain, jabki RAM stale bytes hold karta hai. DMA RAM read karta hai → purana/garbage audio play hota hai. Yeh classic Cache Coherency bug hai.

Mirror case (periph→mem input): CPU ke DMA-filled buffer padhne se pehle, us region ke liye cache invalidate karo taaki CPU stale cached copy ki jagah fresh RAM fetch kare.

Level 5 — Mastery

Exercise 5.1

Full design. Ek sensor node 100 kHz par continuously 12-bit ADC capture karta hai, 16-bit RAM slots mein store karta hai, aur CPU 1000 samples ke blocks process karta hai. Poora DMA setup design karo (saare char SCAM parameters + increment modes + trigger + interrupt strategy), phir verify karo ki CPU ke paas har block process karne ke liye enough time hai, given ki processing $f_{CPU} = 48$ MHz par 50,000 cycles/block karti hai.

Recall Solution 5.1

SCAM setup:

Source $=$ ADC data register, fixed ( $Δ_{S} = 0$ ).
Count $N = 1000$ (ek block).
Address mode: destination increments by $w = 2$ ( $Δ_{D} = 2$ ); source fixed.
Mode/trigger: ADC "conversion ready" DMA request se hardware-triggered — ek beat per sample, naturally rate-matched. Circular / double buffering use karo taaki capture kabhi na ruke: DMA 500 samples par half-transfer interrupt aur 1000 par full-transfer interrupt fire karta hai, halves ping-pong karte hue.

Timing check — kya CPU keep up kar sakta hai?

100 kHz par ek 1000-sample block fill karne ka time: $t_{fill} = \frac{1000}{100 000} = 1 \times 1 0^{- 2} s = 10 ms$
CPU ko ek block process karne ka time: $t_{proc} = \frac{50 000}{48 \times 1 0 ^{6}} \approx 1.042 \times 1 0^{- 3} s \approx 1.04 ms$
Kyunki $t_{proc} = 1.04 ms ≪ t_{fill} = 10 ms$ , CPU ~8.96 ms bachake khatam karta hai har block mein. ✓ System comfortably real-time hai.

CPU utilisation processing ke liye $= t_{proc} / t_{fill} = 1.042/10 \approx 10.4%$ — baaki ~90% doosre tasks ke liye free hai, exactly DMA parallelism ka faida.

Figure — DMA — memory-to-memory, peripheral-to-memory without CPU

Exercise 5.2

Failure analysis. Upar ke design mein, ek engineer ADC ko 800 kHz par set karta hai finer resolution ke liye lekin baki sab same rakhta hai. Processing abhi bhi 50,000 cycles/block karti hai. Kya system abhi bhi deadline meet karta hai? Agar nahi, toh do concrete fixes do.

Recall Solution 5.2

New fill time 800 kHz par: $t_{fill} = \frac{1000}{800 000} = 1.25 \times 1 0^{- 3} s = 1.25 ms$ Processing abhi bhi $t_{proc} \approx 1.04 ms$ chahiye. Ab $t_{proc} / t_{fill} = 1.042/1.25 \approx 83.4%$ — yeh abhi bhi fit hota hai, lekin barely: sirf ~0.21 ms ka slack hai. Koi bhi interrupt jitter, cache miss, ya added work deadline blow kar sakta hai.

Do fixes:

Bigger blocks — 4000 samples per block process karo. Fill time $= 4000/800000 = 5 ms$ ; processing $\approx 4 \times 1.04 = 4.17 ms$ , abhi bhi fit, lekin fixed per-block overhead (interrupt entry, cache invalidate) zyada samples par amortise hota hai, effective per-sample cost kam hoti hai.
Processing optimise karo — cycles/block kam karo (better algorithm, hardware accelerators ka use) taaki $t_{proc}$ $t_{fill}$ se kaafi kam ho jaaye, margin restore ho.

Verify karo ki CPU ADC register khud kabhi touch na kare — DMA saara capture karta hai; CPU sirf transfer-complete interrupt par jaagta hai. Saath hi processing se pehle DMA input buffer par cache invalidate karo (Cache Coherency).

Recall Self-test summary

$t = N c / f$ :::: beats, cycles/beat, clock se transfer time $Throughput = w f / c$ :::: rate ceiling; $N$ cancel ho jaata hai Peripheral side address increment :::: hamesha $Δ = 0$ (fixed register) Periph transfer ka real bottleneck :::: peripheral ki request rate, $w f / c$ nahi CPU ke DMA input padhne se pehle (cache ke saath) :::: cache invalidate karo DMA ke CPU output padhne se pehle (cache ke saath) :::: cache clean/flush karo