Intuition The one core ideaMoving data from place A to place B is boring, repetitive work — and a computer's brain (the CPU) is too valuable to waste on it. DMA is a second, tiny worker made of hardware whose only job is to copy bytes from one address to another while the CPU does real thinking. Everything else on this page is just the vocabulary needed to say where the bytes come from, where they go, how many , and how fast .
This page assumes nothing . Before you can understand the parent note DMA , you need a small pile of words to be crisp in your head. We build each one from a picture, in an order where every word only uses words already defined.
Before "source", "destination", or "address" mean anything, you need to see memory .
Definition Memory & addressMemory is a very long row of tiny boxes, each holding one byte (a number from 0 to 255). Each box has a number stuck to it called its address — like house numbers on a street. To "read" is to look inside a box; to "write" is to put a new number in it.
Look at the figure: the little houses are memory boxes. The number above each house (0, 1, 2, 3 …) is its address — that's how you say which box you mean . The number inside is the data — the actual value stored.
Intuition Why we need addresses at allA copy is nothing but: "take the value in the box here , put it in the box there ." You cannot describe here and there without a way to name boxes. The address is that name. Every DMA symbol below is ultimately a box number or a count of boxes .
Related vault idea: peripherals also live at box numbers — see Memory-Mapped IO .
Definition Byte, word, item widthw byte is one memory box (8 bits, values 0–255). A word is a small group of bytes the machine likes to move together — often 2 or 4 bytes. The item width , written w how many bytes are in one item you choose to move : w = 1 2 4
In the figure, one lavender item of width w = 4
w w = 1 w = 4 entire reason the parent note says wider items are faster — fewer grabs for the same number of bytes.
w Why it feels right: 4 looks like more than 1. The fix: w chunk size per grab , not the total. To move the same total bytes you just do fewer grabs. More on this when we meet N
N B Count N how many items you ask DMA to move. Total bytes B B = N ⋅ w
Worked example Same wall, different bricksMove B = 4096
With w = 1 N = 4096
With w = 4 N = 1024
Same 4096 bytes, but four times fewer grabs the second way. Hold this — the parent's "4× faster" claim falls straight out of it.
S D Source S address you copy from (the box you read). Destination D address you copy to (the box you write). A DMA transfer is, at heart, "read box S D
The coral arrow in the figure points from S D — that arrow is the copy. Everything DMA does is repeating that one arrow N S D
Here is the subtle part the parent note leans on hard, so we build it slowly.
Δ Δ "the change in" — how much a number steps between one moment and the next. So Δ S Δ D
After moving item i S i + 1 = S i + Δ S , D i + 1 = D i + Δ D
Read this out loud: "the next source box is the current source box plus a step Δ S
The figure shows two behaviours side by side:
Both increment (Δ S = Δ D = w memory-to-memory copy, like duplicating a list.Source fixed (Δ S = 0 Δ D = w peripheral-to-memory .
Intuition Why would a source ever stay put?A peripheral (say an ADC ) hands you fresh data through one fixed box — its data register (a memory-mapped address). New readings appear at the same box each time. So you read the same S Δ S = 0 scatter into new destination boxes (Δ D = w
Recall The three directions fromΔ Δ S = Δ D = w Δ S = 0 Δ D = w Δ S = w Δ D = 0
The bus is the one shared road connecting the CPU, the memory, and the DMA engine. Only one traveller can use it at a time, so somebody has to decide who goes — that decider is the arbiter (see Bus Arbitration ).
Picture a one-lane hallway between the CPU's desk and the memory shelves. When DMA is carrying a box down the hallway, the CPU has to wait to fetch its own data. This is why the parent note insists DMA is not free — it is free for the CPU's thinking , but it still occupies the hallway .
Now we can talk about speed — the last group of symbols.
Definition Clock frequencyf clock is a heartbeat that ticks the hardware forward. ==f frequency — how many ticks per second, measured in hertz (Hz). One cycle is one tick. A beat is one item's worth of DMA work (read+write one item), which takes some whole number of cycles c
Worked example Sanity numberN = 1000 c = 1 f = 48 = 48 000 000 t DMA = 48 000 000 1000 × 1 ≈ 20.8 μ s . microsecond -scale job — this is why DMA can keep up with fast peripherals a CPU loop would miss.
Intuition Why "cycles per beat"c c = 1 wait states — so a beat costs more cycles, c > 1 c
An interrupt is a hardware signal that says "stop what you're doing and look at me. " DMA fires a transfer-complete interrupt when the last beat finishes, so the CPU knows the data is now safe to use. (Full mechanism: Interrupts and ISRs .)
Common mistake "I can read the buffer right after starting DMA."Why it feels right: you called start, so it should be done. The fix: DMA runs asynchronously — in the background. You must wait for the transfer-complete interrupt first, or you read half-filled, stale boxes.
Memory as boxes with addresses
Source S and Destination D
Byte word and item width w
Count N and total bytes B
Increments delta S and delta D
Time equals N times c over f
Bus arbitration and stalls
Everything on the left is a word ; everything flows into the single box "DMA transfer" on the right. If any left-hand box is fuzzy, the parent note will feel like magic instead of mechanism.
Cover the right side and answer out loud. If any stumps you, re-read that section above.
What is an address ? The number that names one memory box, so you can say which box you mean.
What is item width w How many bytes are in one item you move per grab (1, 2, or 4).
What is count N B N B = N ⋅ w
What do S D Source (address you read from) and Destination (address you write to).
What does Δ Δ S "Change in"; Δ S = 0
Why is the bus a bottleneck? It's a single shared road — only one of CPU/DMA can use it at a time.
What is f Clock frequency in Hz; one tick lasts 1/ f
Write the DMA transfer-time formula. t DMA = N c / f
Why must you wait for the interrupt before reading? DMA runs in the background; the data isn't complete until the transfer-complete interrupt fires.
