Intuition The ONE core ideaA wire can only carry a voltage that is high or low, changing over time — nothing else. Every communication interface (UART, SPI, I2C, CAN) is just a rulebook deciding how to slice that up-and-down voltage into bits, whose turn it is to talk, and how many wires to use.
This page builds — from absolute zero — every symbol, term and picture the parent topic leans on. Read top to bottom: each idea is a brick the next one stands on.
Before any protocol, understand what a wire is . If you clip an oscilloscope (a "voltage camera") onto a signal wire and its ground, you see a graph: time along the x-axis, voltage up the y-axis .
Definition Logic HIGH and LOWDigital chips agree on two voltage bands . A voltage above a threshold means logic 1 (HIGH) ; below another threshold means logic 0 (LOW) . Everything a chip "says" is a sequence of these two levels in time.
The picture above is the whole subject in one frame: the wire wiggles between two levels, and each protocol is a different way to read meaning out of those wiggles. Keep this graph in your head — every later symbol lives on it.
A bit is one HIGH-or-LOW decision — the smallest piece of information. On our voltage graph it is one time-slot that is either up or down.
A byte is 8 bits grouped together, written like 0x41. The 0x prefix means "read the following as base-16 (hexadecimal)." 0x41 = 4 × 16 + 1 = 65 'A'.
Intuition Why hex, not decimal?One hex digit encodes exactly 4 bits (0000–1111), so two hex digits = one byte, cleanly. Decimal doesn't line up with binary; hex does. That's the only reason it's everywhere in this chapter.
LSB = Least Significant Bit = the bit worth 2 0 = 1 MSB = Most Significant Bit, worth 2 7 = 128 first in time . UART does this; you must know the order to reconstruct the byte.
Common mistake Reading the bits in the wrong orderWhy it feels right: we write numbers MSB-first (left-to-right), so we assume they travel that way. Reality: UART sends LSB-first. If you read left-to-right off the scope you get the byte bit-reversed . Always check which end goes first.
Now that a bit occupies a time-slot, we need to know how wide that slot is.
B Baud B bits/second (bps) speed of the wiggling.
The Greek letter ε Baud rate & clock generation (timers/PLL) for how a chip actually makes this rate from its crystal.
The single deepest split in this whole chapter is: does a separate wire carry the beat?
A clock is a wire that ticks HIGH-LOW-HIGH-LOW at a steady beat. Its edges (the moments it flips) tell the receiver "now — read the data wire this instant."
Definition Synchronous vs Asynchronous
Synchronous = there is a shared clock wire (SPI, I2C). Data is read exactly when the clock ticks — like dancers watching a conductor.Asynchronous = there is no clock wire (UART, CAN). Both sides pre-agree on t bi t
Intuition Why async needs a "starting gun"Without a shared beat, the receiver must know when to start counting . A special first bit (UART's START bit) is the gunshot; then the receiver samples at the middle of each expected slot (see the ↓ arrows in the figure) so small timing errors don't push it into the wrong slot.
Synchronous protocols talk about "which edge ." Here is exactly what an edge is.
Definition Rising / falling edgeA rising edge is the instant a wire goes LOW→HIGH (↑). A falling edge is HIGH→LOW (↓). Chips act on the edge , not the level, because an edge is a sharp, unambiguous moment . This is why SPI's CPOL/CPHA settings (in the parent) are all about which edge samples .
Definition Topology words
Point-to-point : exactly two devices, one wire pair between them (UART).Bus : many devices all tapped onto the same shared wires (I2C, CAN).Master : the device that starts a transfer and (for SPI/I2C) generates the clock.Slave : a device that only responds when spoken to.Multi-master : several devices are each allowed to start a transfer, so we need a rule for collisions.
When many devices share one wire, a new danger appears: two of them driving it at once. That leads straight to the next idea.
Definition Push-pull outputA push-pull output can actively drive the wire both HIGH and LOW — it pushes it up or pulls it down. Great for point-to-point (UART, SPI), fatal on a shared bus: if one chip pushes HIGH while another pulls LOW, you get a short circuit (see left panel — the two arrows fight).
Definition Open-drain output + pull-upAn open-drain output can only pull LOW or let go (float) — it can never push HIGH. A single shared pull-up resistor gently ties the wire to HIGH whenever everyone lets go. So the released state = HIGH, and any device pulling LOW wins with no fight (right panel). This is what makes I2C safe. Full detail in Open-drain vs Push-pull outputs .
Definition Wired-AND logicBecause LOW always wins, the wire's value is HIGH only if every device released it — i.e. the logical AND of all outputs. This is wired-AND , the physics trick behind both I2C addressing and CAN arbitration. See Wired-AND logic .
Open-drain: LOW always wins. A LOW is a hand grabbing the rope; HIGH is everyone letting go. One grab beats a hundred lets-go.
Definition Single-ended signalA single-ended wire's value is its voltage measured against a shared ground. Simple, but any electrical noise that lifts the wire also corrupts the reading (UART, SPI, I2C are single-ended).
Definition Differential signalA differential pair (CAN's CANH, CANL) carries the bit in the difference V C A N H − V C A N L
Intuition Why the difference cancels noiseNoise hits both wires almost equally (they're twisted together). Adding the same jolt + n difference unchanged: ( V H + n ) − ( V L + n ) = V H − V L Differential signaling & noise immunity .
Definition Dominant vs recessiveOn CAN a 0 bit is dominant (actively driven, wins) and a 1 bit is recessive (weak, yields) — wired-AND again, so a 0 from any node overrides a 1. This is how CAN resolves who-talks-first (bitwise arbitration).
Definition Quick symbol glossary
B t bi t = 1/ B ε fractional clock error (e.g. 0.05 = 5% R p Ω C b t r V cc V O L t p r o p L v 2 × 1 0 8
I2C sharing and CAN arbitration
Single-ended vs Differential
Related building blocks in the vault: Serial vs Parallel communication , Shift registers , Interrupts vs Polling , Bit stuffing & CRC in CAN frames .
Cover the right side; can you answer before revealing?
What does a wire physically carry? A voltage that is HIGH or LOW, changing over time — nothing else.
What is one bit? One HIGH-or-LOW decision; the smallest unit of information.
Convert 0x41 to decimal and to a letter. 4 × 16 + 1 = 65 'A'.
What does LSB-first mean? The bit worth 2 0
Give the bit-time formula and t bi t t bi t = 1/ B = 1/9600 ≈ 104.2 μ s
Difference between synchronous and asynchronous? Synchronous has a shared clock wire; asynchronous pre-agrees on bit time and self-times.
What is a rising edge vs a falling edge? Rising = LOW→HIGH (↑); falling = HIGH→LOW (↓).
Why can't two push-pull outputs share one bus wire? One pushing HIGH while the other pulls LOW is a short circuit.
In open-drain, which level always wins and why? LOW — a device can only pull low or float, and the pull-up makes float=HIGH, so any pull-low dominates (wired-AND).
Why does a differential pair reject noise? Noise adds equally to both wires; the receiver reads the difference, so it cancels: ( V H + n ) − ( V L + n ) = V H − V L
On CAN, which bit is dominant, 0 or 1? 0 is dominant (wins); 1 is recessive (yields).
Why is the pull-up rise modelled by e − t / R p C b The wire is an RC circuit charging toward V cc