Communication interfaces — UART, SPI, I2C (master - slave), CAN bus: Question bank

True or false — justify

Each answer starts with True/False but the reason is the point.

UART is called "asynchronous" because it sends no data between bytes

False — "asynchronous" means there is no shared clock wire; timing comes from a pre-agreed baud plus the START-bit starting gun, not from idle gaps.

SPI can address many slaves on the same 4 wires like I2C does

False — SPI has no addressing; the master selects a slave only by pulling that slave's own SS line low, so N slaves need N select lines.

In I2C, driving the bus HIGH is done by a device actively pushing current

False — HIGH is the released (floating) state produced by the pull-up resistor; devices can only pull LOW. That is the essence of open-drain / wired-AND.

On a CAN bus a recessive bit (1) will overwrite a dominant bit (0)

False — dominant (0) always wins; that asymmetry is what makes arbitration resolve to the lowest ID with no corruption.

Differential signalling makes CAN faster than single-ended buses

False — it buys noise immunity, not speed. Noise hits both wires equally and cancels in

V_{C A N H} - V_{C A N L}

; see Differential signaling & noise immunity.

A UART receiver samples each bit at its leading edge

False — it samples at the middle of each bit window (after waiting 1.5 bit-times from the START edge) so small clock mismatch still lands inside the bit.

SPI is inherently half-duplex because there is one data direction per wire

False — MOSI and MISO carry data simultaneously in opposite directions, so SPI is full-duplex: one byte goes out while another comes in.

CAN carries a "send to node 7" destination address in every frame

False — the identifier names the message ("engine RPM"), not a node; interested nodes subscribe, and the same ID sets priority.

I2C's ACK bit is generated by the transmitter to confirm it sent data

False — the receiver pulls SDA low for one clock to acknowledge; a released (HIGH) SDA is a NACK meaning nobody answered.

Spot the error

Each prompt hides one wrong claim — name it and correct it.

"To read from an SPI slave the master just waits; it needn't toggle SCLK."

Wrong — the clock is master-only, so the master must generate clock edges even to read; it clocks dummy bits out on MOSI to shift the slave's data in on MISO.

"Two I2C masters using push-pull outputs is fine as long as they take turns."

Wrong — if both ever drive opposite levels they short and can be damaged; I2C requires open-drain so LOW-wins wired-AND makes simultaneous driving safe.

"UART's effective throughput equals its baud rate."

Wrong — START/STOP (and parity) bits count toward time; for 8N1 a byte costs 10 bits, so useful data throughput is only

8/10

of baud.

"A bigger I2C pull-up resistor is always safer."

Wrong — too large an

R_{p}

slows the RC rise (

t_{r} \approx 0.85 R_{p} C_{b}

) and the bus fails at high speed;

R_{p}

must sit between an upper (rise-time) and lower (sink-current) bound.

"When two CAN nodes collide, both stop and retransmit later."

Wrong — arbitration is non-destructive: the loser backs off mid-ID, the winner keeps going, and the winning message is never re-sent.

"SPI Mode numbers are arbitrary labels with no rule."

Wrong — the mode is exactly (CPOL, CPHA): CPOL sets the idle clock level, CPHA picks first-vs-second sampling edge, giving four defined combinations.

"I2C START is just SDA going low at any time."

Wrong — START is SDA falling while SCL is HIGH; during normal data SDA only changes while SCL is LOW, which is why START is a unique, illegal-during-data event.

Why questions

Why does UART tolerate roughly ±5 % clock error but not much more?

Because sampling error accumulates over the frame; the worst case is the last bit at ~9.5 bit-times, and

9.5 ε < 0.5

gives

ε < 5.3%

before the sample slips out of the bit. See Baud rate & clock generation (timers/PLL).

Why can I2C connect many devices on only two wires while SPI needs 3 + N?

I2C selects devices by a 7-bit address sent on the shared bus, whereas SPI has no addressing and must physically select each slave with its own SS line.

Why does CAN's lowest-ID message win arbitration?

Dominant (0) overrides recessive (1) bit-by-bit; a node sending 1 that reads 0 knows it lost, so more leading zeros (a lower number) survives longer and wins.

Why is the ACK step vital in I2C but absent in SPI?

I2C addresses devices blindly on a shared bus, so it needs the ACK to confirm someone actually answered; SPI's dedicated SS line already guarantees a specific chip is listening.

Why does differential signalling let CAN survive a car's electrical noise?

Interference is common-mode — it lands on CANH and CANL equally — and the receiver reads only their difference, so the shared noise subtracts to zero.

Why does bus length limit CAN's bit rate?

A dominant bit must propagate to the far node and back within one bit so the loser detects its loss in time, forcing

t_{bi t} \geq 2 L / v

; longer wire means slower bits.

Why are UART and SPI actively driven while I2C is open-drain?

UART is point-to-point and SPI is single-master, so exactly one driver owns each line; I2C is multi-master on a shared line, so it needs release-to-HIGH open-drain to avoid shorts.

Edge cases

What happens on I2C if you forget the pull-up resistors entirely?

Nothing can pull the line to a defined HIGH, so SDA/SCL float; reads return garbage or the bus latches stuck, because open-drain devices can only pull LOW, never drive HIGH.

At exactly the maximum tolerated UART clock drift, where does the sample land?

At the very edge of the last bit's window — any more drift and the final bit is sampled outside its interval, corrupting the byte; this is why designers keep a margin below 5 %.

If two CAN nodes transmit identical IDs simultaneously, who wins?

Neither loses during ID arbitration since every bit matches; the collision only surfaces later (data phase), so CAN requires that IDs be unique per transmitter to keep arbitration deterministic.

An I2C master sends an address and gets a NACK (SDA stays HIGH) — what does that mean?

No device on the bus recognised that address (nobody pulled SDA low), so the addressed slave is absent, wrong, or busy; the master should abort with STOP.

You daisy-chain SPI slaves to save SS lines — what changed about the data path?

The slaves' shift registers are now linked end-to-end into one long ring, so a byte ripples through every device before returning; this trades per-slave selection for longer clocked-out sequences, and only works if devices support the mode.

What is the SPI bus state right after the master raises SS?

The selected slave is deselected and releases MISO, so the bus is idle and free for the master to select a different slave — deselection is what frees a shared SPI bus.

If a UART sender and receiver disagree on baud by 20 %, what does the receiver read?

Its mid-bit sample points drift far off within a few bits and it latches wrong levels, producing framing errors or garbage — well outside the ~5 % tolerance the frame can absorb.

Recall One-line reflexes

UART timing source ::: pre-agreed baud + START-bit starting gun, no clock wire SPI slave selection ::: one active-LOW SS line per slave I2C HIGH is produced by ::: the pull-up resistor (open-drain release) CAN winning bit ::: dominant (0) beats recessive (1) CAN address names ::: the message, not the node