Communication interfaces — UART, SPI, I2C (master - slave), CAN bus: Question bank

5.5.5 · D5 · Coding › Embedded Systems & Real-Time Software › Communication interfaces — UART, SPI, I2C (master - slave),

True or false — justify karo

Har jawab True/False se shuru hota hai lekin reason hi asli point hai.

UART ko "asynchronous" isliye kehte hain kyunki woh bytes ke beech koi data nahi bhejta

False — "asynchronous" ka matlab hai ki koi shared clock wire nahi hoti; timing ek pre-agreed baud aur START-bit ke starting gun se aati hai, idle gaps se nahi.

SPI ek hi 4 wires pe I2C ki tarah kaafi saare slaves ko address kar sakta hai

False — SPI mein koi addressing nahi hoti; master ek slave ko sirf uski apni SS line ko low karke select karta hai, isliye N slaves ke liye N select lines chahiye.

I2C mein, bus ko HIGH drive karna ek device ke actively current push karne se hota hai

False — HIGH ek released (floating) state hoti hai jo pull-up resistor produce karta hai; devices sirf LOW pull kar sakti hain. Yahi open-drain / wired-AND ka essence hai.

CAN bus pe ek recessive bit (1) ek dominant bit (0) ko overwrite kar deta hai

False — dominant (0) hamesha jeet ta hai; yahi asymmetry hai jo arbitration ko lowest ID pe resolve karti hai bina kisi corruption ke.

Differential signalling CAN ko single-ended buses se faster banata hai

False — ye noise immunity deta hai, speed nahi. Noise dono wires ko equally hit karti hai aur

V_{C A N H} - V_{C A N L}

mein cancel ho jaati hai; dekho Differential signaling & noise immunity.

Ek UART receiver har bit ko uski leading edge pe sample karta hai

False — woh har bit window ke middle mein sample karta hai (START edge se 1.5 bit-times baad wait karke) taaki clock mismatch phir bhi bit ke andar land kare.

SPI inherently half-duplex hota hai kyunki ek wire pe ek hi data direction hoti hai

False — MOSI aur MISO ek saath opposite directions mein data carry karte hain, isliye SPI full-duplex hai: ek byte bahar jaata hai jabki doosra andar aata hai.

CAN har frame mein ek "node 7 ko bhejo" wali destination address carry karta hai

False — identifier message ka naam hota hai ("engine RPM"), node ka nahi; interested nodes subscribe karte hain, aur wohi ID priority bhi set karta hai.

I2C ka ACK bit transmitter dwara generate hota hai yeh confirm karne ke liye ki usne data bheja

False — receiver acknowledge karne ke liye ek clock ke liye SDA low pull karta hai; released (HIGH) SDA ek NACK hai jiska matlab hai kisi ne jawab nahi diya.

Error dhundho

Har prompt mein ek galat claim chhupa hai — use naam do aur correct karo.

"SPI slave se read karne ke liye master sirf wait karta hai; use SCLK toggle karne ki zaroorat nahi."

Galat — clock sirf master ki hoti hai, isliye master ko read ke liye bhi clock edges generate karni padti hain; woh MOSI pe dummy bits clock out karta hai taaki slave ka data MISO pe shift in ho sake.

"Do I2C masters push-pull outputs ke saath theek hain jab tak woh baari baari lein."

Galat — agar dono kabhi bhi opposite levels drive karein toh short circuit ho sakta hai aur damage ho sakta hai; I2C requires open-drain taaki LOW-wins wired-AND simultaneous driving ko safe banaye.

"UART ki effective throughput uski baud rate ke barabar hoti hai."

Galat — START/STOP (aur parity) bits time mein count hote hain; 8N1 mein ek byte 10 bits leta hai, isliye useful data throughput sirf baud ka

8/10

hoti hai.

"Bada I2C pull-up resistor hamesha zyada safe hota hai."

Galat — bahut bada

R_{p}

RC rise ko slow kar deta hai (

t_{r} \approx 0.85 R_{p} C_{b}

) aur bus high speed pe fail kar deti hai;

R_{p}

ek upper (rise-time) aur lower (sink-current) bound ke beech hona chahiye.

"Jab do CAN nodes collide karte hain, dono ruk jaate hain aur baad mein retransmit karte hain."

Galat — arbitration non-destructive hoti hai: loser mid-ID pe back off karta hai, winner chalata rehta hai, aur winning message kabhi re-send nahi hota.

"SPI Mode numbers arbitrary labels hain jinmein koi rule nahi."

Galat — mode exactly (CPOL, CPHA) hota hai: CPOL idle clock level set karta hai, CPHA first-vs-second sampling edge choose karta hai, jo chaar defined combinations deta hai.

"I2C START bas kisi bhi time pe SDA ka low jaana hai."

Galat — START tab hota hai jab SDA SCL HIGH rehte hue fall kare; normal data ke dauran SDA sirf tab badalti hai jab SCL LOW ho, isliye START ek unique, data-ke-dauran-illegal event hai.

Why questions

UART roughly ±5% clock error kyun tolerate karta hai lekin zyada nahi?

Kyunki sampling error frame pe accumulate hoti hai; worst case last bit ke liye ~9.5 bit-times pe hota hai, aur

9.5 ε < 0.5

ε < 5.3%

milta hai jisse pehle sample bit se bahar slip ho. Dekho Baud rate & clock generation (timers/PLL).

I2C sirf do wires pe kaafi saari devices connect kyun kar sakta hai jabki SPI ko 3 + N chahiye?

I2C devices ko shared bus pe bheje gaye 7-bit address se select karta hai, jabki SPI mein koi addressing nahi hoti aur har slave ko apni dedicated SS line chahiye.

CAN ka lowest-ID message arbitration kyun jeetta hai?

Dominant (0) bit-by-bit recessive (1) ko override karta hai; ek node jo 1 bhej raha hai lekin 0 padh raha hai jaanta hai ki woh haar gaya, isliye zyada leading zeros (ek chhota number) zyada der tak survive karta hai aur jeetta hai.

I2C mein ACK step kyun zaroori hai lekin SPI mein nahi?

I2C shared bus pe devices ko blindly address karta hai, isliye use ACK chahiye taaki confirm ho ki kisine jawab diya; SPI ki dedicated SS line already guarantee karti hai ki ek specific chip sun raha hai.

Differential signalling CAN ko gaadi ke electrical noise mein survive kyun karne deta hai?

Interference common-mode hoti hai — woh CANH aur CANL pe equally land karti hai — aur receiver sirf unka difference padhta hai, isliye shared noise subtract hokar zero ho jaata hai.

Bus length CAN ki bit rate ko kyun limit karti hai?

Ek dominant bit ko door wale node tak pahunchna aur wapas aana hoga ek bit ke andar taaki loser apna loss time pe detect kar sake, jo force karta hai

t_{bi t} \geq 2 L / v

; lambi wire matlab slow bits.

UART aur SPI actively driven kyun hain jabki I2C open-drain hai?

UART point-to-point hai aur SPI single-master hai, isliye exactly ek driver har line own karta hai; I2C multi-master hai shared line pe, isliye shorts avoid karne ke liye release-to-HIGH open-drain chahiye.

Edge cases

Agar I2C mein pull-up resistors hi bhool jao toh kya hota hai?

Kuch bhi line ko ek defined HIGH tak pull nahi kar sakta, isliye SDA/SCL float karte hain; reads garbage return karte hain ya bus stuck latch ho jaata hai, kyunki open-drain devices sirf LOW pull kar sakti hain, kabhi HIGH drive nahi kar sakti.

Exactly maximum tolerated UART clock drift pe, sample kahan land karta hai?

Last bit ki window ke bilkul edge pe — thodi si aur drift aur final bit apne interval ke bahar sample hogi, byte corrupt ho jaayegi; isliye designers 5% se neeche margin rakhte hain.

Agar do CAN nodes ek saath identical IDs transmit karein, kaun jeet ta hai?

ID arbitration ke dauran koi nahi haarta kyunki har bit match karti hai; collision baad mein (data phase mein) surface hoti hai, isliye CAN require karta hai ki IDs har transmitter ke liye unique hon taaki arbitration deterministic rahe.

Ek I2C master ek address bhejta hai aur NACK milta hai (SDA HIGH rehta hai) — iska kya matlab hai?

Bus pe kisi bhi device ne woh address recognize nahi kiya (kisine SDA low nahi kheeencha), isliye addressed slave absent, galat, ya busy hai; master ko STOP ke saath abort karna chahiye.

Agar SS lines bachane ke liye SPI slaves ko daisy-chain karo — data path mein kya badla?

Slaves ke shift registers ab end-to-end ek lambi ring mein jud gaye hain, isliye ek byte har device mein ripple karta hai wapas aane se pehle; ye per-slave selection ke badle longer clocked-out sequences ki trade karta hai, aur sirf tab kaam karta hai jab devices woh mode support karein.

Master ke SS raise karne ke turant baad SPI bus ki state kya hoti hai?

Selected slave deselect ho jaata hai aur MISO release kar deta hai, isliye bus idle aur free hoti hai master ke liye koi doosra slave select karne ke liye — deselection hi shared SPI bus ko free karti hai.

Agar UART sender aur receiver baud mein 20% se disagree karein, receiver kya padh ta hai?

Uske mid-bit sample points kuch bits ke andar bahut dur drift kar jaate hain aur woh galat levels latch karta hai, framing errors ya garbage produce karta hai — yeh frame ke ~5% tolerance se kaafi bahar hai.

Recall One-line reflexes

UART timing source ::: pre-agreed baud + START-bit starting gun, koi clock wire nahi SPI slave selection ::: har slave ke liye ek active-LOW SS line I2C HIGH produce hoti hai ::: pull-up resistor se (open-drain release) CAN winning bit ::: dominant (0) beats recessive (1) CAN address naam deta hai ::: message ko, node ko nahi